1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2020 Marvell International Ltd.
6 #include "cn9130.dtsi" /* include SoC device tree */
8 #include <dt-bindings/gpio/gpio.h>
12 stdout-path = "serial0:115200n8";
17 ethernet0 = &cp0_eth0;
18 ethernet1 = &cp0_eth1;
19 ethernet2 = &cp0_eth2;
25 device_type = "memory";
26 reg = <0x0 0x0 0x0 0x80000000>;
29 ap0_reg_mmc_vccq: ap0_mmc_vccq@0 {
30 compatible = "regulator-gpio";
31 regulator-name = "ap0_mmc_vccq";
32 regulator-min-microvolt = <1800000>;
33 regulator-max-microvolt = <3300000>;
34 gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
39 cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
40 compatible = "regulator-fixed";
41 regulator-name = "cp0-xhci1-vbus";
42 regulator-min-microvolt = <5000000>;
43 regulator-max-microvolt = <5000000>;
45 gpio = <&expander0 8 GPIO_ACTIVE_HIGH>;
48 cp0_usb3_0_phy0: cp0_usb3_phy0 {
49 compatible = "usb-nop-xceiv";
52 cp0_usb3_0_phy1: cp0_usb3_phy1 {
53 compatible = "usb-nop-xceiv";
54 vcc-supply = <&cp0_reg_usb3_vbus1>;
57 cp0_reg_sd_vccq: cp0_sd_vccq@0 {
58 compatible = "regulator-gpio";
59 regulator-name = "cp0_sd_vccq";
60 regulator-min-microvolt = <1800000>;
61 regulator-max-microvolt = <3300000>;
62 gpios = <&cp0_gpio2 18 GPIO_ACTIVE_HIGH>;
67 cp0_reg_sd_vcc: cp0_sd_vcc@0 {
68 compatible = "regulator-fixed";
69 regulator-name = "cp0_sd_vcc";
70 regulator-min-microvolt = <3300000>;
71 regulator-max-microvolt = <3300000>;
72 gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
78 compatible = "sff,sfp";
79 i2c-bus = <&cp0_i2c1>;
80 mod-def0-gpios = <&expander0 3 GPIO_ACTIVE_LOW>;
81 los-gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
82 tx-disable-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>;
83 tx-fault-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_HIGH>;
84 maximum-power-milliwatt = <3000>;
93 /* on-board eMMC U6 */
95 pinctrl-names = "default";
99 vqmmc-supply = <&ap0_reg_mmc_vccq>;
103 cp0_pinctrl: pinctrl {
104 compatible = "marvell,cp115-standalone-pinctrl";
106 cp0_i2c0_pins: cp0-i2c-pins-0 {
107 marvell,pins = "mpp37", "mpp38";
108 marvell,function = "i2c0";
110 cp0_i2c1_pins: cp0-i2c-pins-1 {
111 marvell,pins = "mpp35", "mpp36";
112 marvell,function = "i2c1";
114 cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
115 marvell,pins = "mpp55";
116 marvell,function = "gpio";
118 cp0_sdhci_pins: cp0-sdhi-pins-0 {
119 marvell,pins = "mpp56", "mpp57", "mpp58",
120 "mpp59", "mpp60", "mpp61";
121 marvell,function = "sdio";
123 cp0_spi1_pins: cp0-spi-pins-1 {
124 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
125 marvell,function = "spi1";
139 pinctrl-names = "default";
140 pinctrl-0 = <&cp0_i2c0_pins>;
142 clock-frequency = <100000>;
143 expander0: mcp23x17@20 {
144 compatible = "microchip,mcp23017";
153 pinctrl-names = "default";
154 pinctrl-0 = <&cp0_i2c1_pins>;
155 clock-frequency = <100000>;
161 pinctrl-names = "default";
162 pinctrl-0 = <&cp0_sdhci_pins
163 &cp0_sdhci_cd_pins_crb>;
165 cd-gpios = <&cp0_gpio2 23 GPIO_ACTIVE_HIGH>;
166 vqmmc-supply = <&cp0_reg_sd_vccq>;
167 vmmc-supply = <&cp0_reg_sd_vcc>;
172 pinctrl-names = "default";
173 pinctrl-0 = <&cp0_spi1_pins>;
174 reg = <0x700680 0x50>, /* control */
175 <0x2000000 0x1000000>; /* CS0 */
179 #address-cells = <0x1>;
181 compatible = "jedec,spi-nor";
183 /* On-board MUX does not allow higher frequencies */
184 spi-max-frequency = <40000000>;
187 compatible = "fixed-partitions";
188 #address-cells = <1>;
193 reg = <0x0 0x200000>;
197 label = "Filesystem";
198 reg = <0x200000 0xe00000>;
206 phy0: ethernet-phy@0 {
211 /* Actual device is MV88E6393X */
212 compatible = "marvell,mv88e6190";
213 #address-cells = <1>;
216 interrupt-parent = <&cp0_gpio1>;
217 interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
218 interrupt-controller;
219 #interrupt-cells = <2>;
224 #address-cells = <1>;
230 phy-handle = <&switch0phy1>;
236 phy-handle = <&switch0phy2>;
242 phy-handle = <&switch0phy3>;
248 phy-handle = <&switch0phy4>;
254 phy-handle = <&switch0phy5>;
260 phy-handle = <&switch0phy6>;
266 phy-handle = <&switch0phy7>;
272 phy-handle = <&switch0phy8>;
278 phy-mode = "10gbase-r";
280 managed = "in-band-status";
285 ethernet = <&cp0_eth0>;
286 phy-mode = "10gbase-r";
287 managed = "in-band-status";
293 #address-cells = <1>;
296 switch0phy1: switch0phy1@1 {
300 switch0phy2: switch0phy2@2 {
304 switch0phy3: switch0phy3@3 {
308 switch0phy4: switch0phy4@4 {
312 switch0phy5: switch0phy5@5 {
316 switch0phy6: switch0phy6@6 {
320 switch0phy7: switch0phy7@7 {
324 switch0phy8: switch0phy8@8 {
333 nbaset_phy0: ethernet-phy@0 {
334 compatible = "ethernet-phy-ieee802.3-c45";
344 /* This port is connected to 88E6393X switch */
346 phy-mode = "10gbase-r";
347 managed = "in-band-status";
348 phys = <&cp0_comphy4 0>;
354 phy-mode = "rgmii-id";
358 /* This port uses "2500base-t" phy-mode */
360 phy = <&nbaset_phy0>;
361 phys = <&cp0_comphy5 2>;