1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
5 * Device Tree file for Marvell Armada CP110.
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
13 #define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000))
14 #define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000))
15 #define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
19 * The contents of the node are defined below, in order to
20 * save one indentation level
22 CP110_NAME: CP110_NAME { };
25 * CPs only have one sensor in the thermal IC.
27 * The cooling maps are empty as there are no cooling devices.
30 CP110_LABEL(thermal_ic): CP110_NODE_NAME(thermal-ic) {
31 polling-delay-passive = <0>; /* Interrupt driven */
32 polling-delay = <0>; /* Interrupt driven */
34 thermal-sensors = <&CP110_LABEL(thermal) 0>;
37 CP110_LABEL(crit): crit {
38 temperature = <100000>; /* mC degrees */
39 hysteresis = <2000>; /* mC degrees */
52 compatible = "simple-bus";
53 interrupt-parent = <&CP110_LABEL(icu_nsr)>;
56 config-space@CP110_BASE {
59 compatible = "simple-bus";
60 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
62 CP110_LABEL(ethernet): ethernet@0 {
63 compatible = "marvell,armada-7k-pp22";
64 reg = <0x0 0x100000>, <0x129000 0xb000>;
65 clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
66 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
67 <&CP110_LABEL(clk) 1 18>;
68 clock-names = "pp_clk", "gop_clk",
69 "mg_clk", "mg_core_clk", "axi_clk";
70 marvell,system-controller = <&CP110_LABEL(syscon0)>;
74 CP110_LABEL(eth0): eth0 {
75 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
76 <43 IRQ_TYPE_LEVEL_HIGH>,
77 <47 IRQ_TYPE_LEVEL_HIGH>,
78 <51 IRQ_TYPE_LEVEL_HIGH>,
79 <55 IRQ_TYPE_LEVEL_HIGH>,
80 <59 IRQ_TYPE_LEVEL_HIGH>,
81 <63 IRQ_TYPE_LEVEL_HIGH>,
82 <67 IRQ_TYPE_LEVEL_HIGH>,
83 <71 IRQ_TYPE_LEVEL_HIGH>,
84 <129 IRQ_TYPE_LEVEL_HIGH>;
85 interrupt-names = "hif0", "hif1", "hif2",
86 "hif3", "hif4", "hif5", "hif6", "hif7",
93 CP110_LABEL(eth1): eth1 {
94 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
95 <44 IRQ_TYPE_LEVEL_HIGH>,
96 <48 IRQ_TYPE_LEVEL_HIGH>,
97 <52 IRQ_TYPE_LEVEL_HIGH>,
98 <56 IRQ_TYPE_LEVEL_HIGH>,
99 <60 IRQ_TYPE_LEVEL_HIGH>,
100 <64 IRQ_TYPE_LEVEL_HIGH>,
101 <68 IRQ_TYPE_LEVEL_HIGH>,
102 <72 IRQ_TYPE_LEVEL_HIGH>,
103 <128 IRQ_TYPE_LEVEL_HIGH>;
104 interrupt-names = "hif0", "hif1", "hif2",
105 "hif3", "hif4", "hif5", "hif6", "hif7",
112 CP110_LABEL(eth2): eth2 {
113 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
114 <45 IRQ_TYPE_LEVEL_HIGH>,
115 <49 IRQ_TYPE_LEVEL_HIGH>,
116 <53 IRQ_TYPE_LEVEL_HIGH>,
117 <57 IRQ_TYPE_LEVEL_HIGH>,
118 <61 IRQ_TYPE_LEVEL_HIGH>,
119 <65 IRQ_TYPE_LEVEL_HIGH>,
120 <69 IRQ_TYPE_LEVEL_HIGH>,
121 <73 IRQ_TYPE_LEVEL_HIGH>,
122 <127 IRQ_TYPE_LEVEL_HIGH>;
123 interrupt-names = "hif0", "hif1", "hif2",
124 "hif3", "hif4", "hif5", "hif6", "hif7",
132 CP110_LABEL(comphy): phy@120000 {
133 compatible = "marvell,comphy-cp110";
134 reg = <0x120000 0x6000>;
135 marvell,system-controller = <&CP110_LABEL(syscon0)>;
136 clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
137 <&CP110_LABEL(clk) 1 18>;
138 clock-names = "mg_clk", "mg_core_clk", "axi_clk";
139 #address-cells = <1>;
142 CP110_LABEL(comphy0): phy@0 {
147 CP110_LABEL(comphy1): phy@1 {
152 CP110_LABEL(comphy2): phy@2 {
157 CP110_LABEL(comphy3): phy@3 {
162 CP110_LABEL(comphy4): phy@4 {
167 CP110_LABEL(comphy5): phy@5 {
173 CP110_LABEL(mdio): mdio@12a200 {
174 #address-cells = <1>;
176 compatible = "marvell,orion-mdio";
177 reg = <0x12a200 0x10>;
178 clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>,
179 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
183 CP110_LABEL(xmdio): mdio@12a600 {
184 #address-cells = <1>;
186 compatible = "marvell,xmdio";
187 reg = <0x12a600 0x10>;
188 clocks = <&CP110_LABEL(clk) 1 5>,
189 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
193 CP110_LABEL(icu): interrupt-controller@1e0000 {
194 compatible = "marvell,cp110-icu";
195 reg = <0x1e0000 0x440>;
196 #address-cells = <1>;
199 CP110_LABEL(icu_nsr): interrupt-controller@10 {
200 compatible = "marvell,cp110-icu-nsr";
202 #interrupt-cells = <2>;
203 interrupt-controller;
204 msi-parent = <&gicp>;
207 CP110_LABEL(icu_sei): interrupt-controller@50 {
208 compatible = "marvell,cp110-icu-sei";
210 #interrupt-cells = <2>;
211 interrupt-controller;
216 CP110_LABEL(rtc): rtc@284000 {
217 compatible = "marvell,armada-8k-rtc";
218 reg = <0x284000 0x20>, <0x284080 0x24>;
219 reg-names = "rtc", "rtc-soc";
220 interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
223 CP110_LABEL(syscon0): system-controller@440000 {
224 compatible = "syscon", "simple-mfd";
225 reg = <0x440000 0x2000>;
227 CP110_LABEL(clk): clock {
228 compatible = "marvell,cp110-clock";
232 CP110_LABEL(gpio1): gpio@100 {
233 compatible = "marvell,armada-8k-gpio";
238 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
239 interrupt-controller;
240 interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
241 <85 IRQ_TYPE_LEVEL_HIGH>,
242 <84 IRQ_TYPE_LEVEL_HIGH>,
243 <83 IRQ_TYPE_LEVEL_HIGH>;
244 #interrupt-cells = <2>;
248 CP110_LABEL(gpio2): gpio@140 {
249 compatible = "marvell,armada-8k-gpio";
254 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
255 interrupt-controller;
256 interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
257 <81 IRQ_TYPE_LEVEL_HIGH>,
258 <80 IRQ_TYPE_LEVEL_HIGH>,
259 <79 IRQ_TYPE_LEVEL_HIGH>;
260 #interrupt-cells = <2>;
265 CP110_LABEL(syscon1): system-controller@400000 {
266 compatible = "syscon", "simple-mfd";
267 reg = <0x400000 0x1000>;
268 #address-cells = <1>;
271 CP110_LABEL(thermal): thermal-sensor@70 {
272 compatible = "marvell,armada-cp110-thermal";
274 interrupts-extended =
275 <&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
276 #thermal-sensor-cells = <1>;
280 CP110_LABEL(usb3_0): usb3@500000 {
281 compatible = "marvell,armada-8k-xhci",
283 reg = <0x500000 0x4000>;
285 interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
286 clock-names = "core", "reg";
287 clocks = <&CP110_LABEL(clk) 1 22>,
288 <&CP110_LABEL(clk) 1 16>;
292 CP110_LABEL(usb3_1): usb3@510000 {
293 compatible = "marvell,armada-8k-xhci",
295 reg = <0x510000 0x4000>;
297 interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
298 clock-names = "core", "reg";
299 clocks = <&CP110_LABEL(clk) 1 23>,
300 <&CP110_LABEL(clk) 1 16>;
304 CP110_LABEL(sata0): sata@540000 {
305 compatible = "marvell,armada-8k-ahci",
307 reg = <0x540000 0x30000>;
309 interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&CP110_LABEL(clk) 1 15>,
311 <&CP110_LABEL(clk) 1 16>;
312 #address-cells = <1>;
325 CP110_LABEL(xor0): xor@6a0000 {
326 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
327 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
329 msi-parent = <&gic_v2m0>;
330 clock-names = "core", "reg";
331 clocks = <&CP110_LABEL(clk) 1 8>,
332 <&CP110_LABEL(clk) 1 14>;
335 CP110_LABEL(xor1): xor@6c0000 {
336 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
337 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
339 msi-parent = <&gic_v2m0>;
340 clock-names = "core", "reg";
341 clocks = <&CP110_LABEL(clk) 1 7>,
342 <&CP110_LABEL(clk) 1 14>;
345 CP110_LABEL(spi0): spi@700600 {
346 compatible = "marvell,armada-380-spi";
347 reg = <0x700600 0x50>;
348 #address-cells = <0x1>;
350 clock-names = "core", "axi";
351 clocks = <&CP110_LABEL(clk) 1 21>,
352 <&CP110_LABEL(clk) 1 17>;
356 CP110_LABEL(spi1): spi@700680 {
357 compatible = "marvell,armada-380-spi";
358 reg = <0x700680 0x50>;
359 #address-cells = <1>;
361 clock-names = "core", "axi";
362 clocks = <&CP110_LABEL(clk) 1 21>,
363 <&CP110_LABEL(clk) 1 17>;
367 CP110_LABEL(i2c0): i2c@701000 {
368 compatible = "marvell,mv78230-i2c";
369 reg = <0x701000 0x20>;
370 #address-cells = <1>;
372 interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
373 clock-names = "core", "reg";
374 clocks = <&CP110_LABEL(clk) 1 21>,
375 <&CP110_LABEL(clk) 1 17>;
379 CP110_LABEL(i2c1): i2c@701100 {
380 compatible = "marvell,mv78230-i2c";
381 reg = <0x701100 0x20>;
382 #address-cells = <1>;
384 interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
385 clock-names = "core", "reg";
386 clocks = <&CP110_LABEL(clk) 1 21>,
387 <&CP110_LABEL(clk) 1 17>;
391 CP110_LABEL(uart0): serial@702000 {
392 compatible = "snps,dw-apb-uart";
393 reg = <0x702000 0x100>;
395 interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
397 clock-names = "baudclk", "apb_pclk";
398 clocks = <&CP110_LABEL(clk) 1 21>,
399 <&CP110_LABEL(clk) 1 17>;
403 CP110_LABEL(uart1): serial@702100 {
404 compatible = "snps,dw-apb-uart";
405 reg = <0x702100 0x100>;
407 interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
409 clock-names = "baudclk", "apb_pclk";
410 clocks = <&CP110_LABEL(clk) 1 21>,
411 <&CP110_LABEL(clk) 1 17>;
415 CP110_LABEL(uart2): serial@702200 {
416 compatible = "snps,dw-apb-uart";
417 reg = <0x702200 0x100>;
419 interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
421 clock-names = "baudclk", "apb_pclk";
422 clocks = <&CP110_LABEL(clk) 1 21>,
423 <&CP110_LABEL(clk) 1 17>;
427 CP110_LABEL(uart3): serial@702300 {
428 compatible = "snps,dw-apb-uart";
429 reg = <0x702300 0x100>;
431 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
433 clock-names = "baudclk", "apb_pclk";
434 clocks = <&CP110_LABEL(clk) 1 21>,
435 <&CP110_LABEL(clk) 1 17>;
439 CP110_LABEL(nand_controller): nand@720000 {
441 * Due to the limitation of the pins available
442 * this controller is only usable on the CPM
443 * for A7K and on the CPS for A8K.
445 compatible = "marvell,armada-8k-nand-controller",
446 "marvell,armada370-nand-controller";
447 reg = <0x720000 0x54>;
448 #address-cells = <1>;
450 interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
451 clock-names = "core", "reg";
452 clocks = <&CP110_LABEL(clk) 1 2>,
453 <&CP110_LABEL(clk) 1 17>;
454 marvell,system-controller = <&CP110_LABEL(syscon0)>;
458 CP110_LABEL(trng): trng@760000 {
459 compatible = "marvell,armada-8k-rng",
460 "inside-secure,safexcel-eip76";
461 reg = <0x760000 0x7d>;
462 interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
463 clock-names = "core", "reg";
464 clocks = <&CP110_LABEL(clk) 1 25>,
465 <&CP110_LABEL(clk) 1 17>;
469 CP110_LABEL(sdhci0): sdhci@780000 {
470 compatible = "marvell,armada-cp110-sdhci";
471 reg = <0x780000 0x300>;
472 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
473 clock-names = "core", "axi";
474 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
479 CP110_LABEL(crypto): crypto@800000 {
480 compatible = "inside-secure,safexcel-eip197b";
481 reg = <0x800000 0x200000>;
482 interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
483 <88 IRQ_TYPE_LEVEL_HIGH>,
484 <89 IRQ_TYPE_LEVEL_HIGH>,
485 <90 IRQ_TYPE_LEVEL_HIGH>,
486 <91 IRQ_TYPE_LEVEL_HIGH>,
487 <92 IRQ_TYPE_LEVEL_HIGH>;
488 interrupt-names = "mem", "ring0", "ring1",
489 "ring2", "ring3", "eip";
490 clock-names = "core", "reg";
491 clocks = <&CP110_LABEL(clk) 1 26>,
492 <&CP110_LABEL(clk) 1 17>;
497 CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
498 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
499 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
500 <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
501 reg-names = "ctrl", "config";
502 #address-cells = <3>;
504 #interrupt-cells = <1>;
507 msi-parent = <&gic_v2m0>;
509 bus-range = <0 0xff>;
512 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000
513 /* non-prefetchable memory */
514 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
515 interrupt-map-mask = <0 0 0 0>;
516 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
517 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
519 clock-names = "core", "reg";
520 clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
524 CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
525 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
526 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
527 <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
528 reg-names = "ctrl", "config";
529 #address-cells = <3>;
531 #interrupt-cells = <1>;
534 msi-parent = <&gic_v2m0>;
536 bus-range = <0 0xff>;
539 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000
540 /* non-prefetchable memory */
541 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
542 interrupt-map-mask = <0 0 0 0>;
543 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
544 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
547 clock-names = "core", "reg";
548 clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
552 CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
553 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
554 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
555 <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
556 reg-names = "ctrl", "config";
557 #address-cells = <3>;
559 #interrupt-cells = <1>;
562 msi-parent = <&gic_v2m0>;
564 bus-range = <0 0xff>;
567 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000
568 /* non-prefetchable memory */
569 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
570 interrupt-map-mask = <0 0 0 0>;
571 interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
572 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
575 clock-names = "core", "reg";
576 clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;