1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
5 * Device Tree file for Marvell Armada CP110.
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
10 #include "armada-common.dtsi"
12 #define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000))
13 #define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000))
14 #define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
18 * The contents of the node are defined below, in order to
19 * save one indentation level
21 CP110_NAME: CP110_NAME { };
27 compatible = "simple-bus";
28 interrupt-parent = <&CP110_LABEL(icu)>;
31 config-space@CP110_BASE {
34 compatible = "simple-bus";
35 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
37 CP110_LABEL(ethernet): ethernet@0 {
38 compatible = "marvell,armada-7k-pp22";
39 reg = <0x0 0x100000>, <0x129000 0xb000>;
40 clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
41 <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
42 <&CP110_LABEL(clk) 1 18>;
43 clock-names = "pp_clk", "gop_clk",
44 "mg_clk", "mg_core_clk", "axi_clk";
45 marvell,system-controller = <&CP110_LABEL(syscon0)>;
49 CP110_LABEL(eth0): eth0 {
50 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
51 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
52 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
53 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
54 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
55 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
56 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
57 "tx-cpu3", "rx-shared", "link";
63 CP110_LABEL(eth1): eth1 {
64 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
65 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
66 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
67 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
68 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
69 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
70 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
71 "tx-cpu3", "rx-shared", "link";
77 CP110_LABEL(eth2): eth2 {
78 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
79 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
80 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
81 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
82 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
83 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
84 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
85 "tx-cpu3", "rx-shared", "link";
92 CP110_LABEL(comphy): phy@120000 {
93 compatible = "marvell,comphy-cp110";
94 reg = <0x120000 0x6000>;
95 marvell,system-controller = <&CP110_LABEL(syscon0)>;
99 CP110_LABEL(comphy0): phy@0 {
104 CP110_LABEL(comphy1): phy@1 {
109 CP110_LABEL(comphy2): phy@2 {
114 CP110_LABEL(comphy3): phy@3 {
119 CP110_LABEL(comphy4): phy@4 {
124 CP110_LABEL(comphy5): phy@5 {
130 CP110_LABEL(mdio): mdio@12a200 {
131 #address-cells = <1>;
133 compatible = "marvell,orion-mdio";
134 reg = <0x12a200 0x10>;
135 clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>,
136 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
140 CP110_LABEL(xmdio): mdio@12a600 {
141 #address-cells = <1>;
143 compatible = "marvell,xmdio";
144 reg = <0x12a600 0x10>;
145 clocks = <&CP110_LABEL(clk) 1 5>,
146 <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
150 CP110_LABEL(icu): interrupt-controller@1e0000 {
151 compatible = "marvell,cp110-icu";
152 reg = <0x1e0000 0x440>;
153 #interrupt-cells = <3>;
154 interrupt-controller;
155 msi-parent = <&gicp>;
158 CP110_LABEL(rtc): rtc@284000 {
159 compatible = "marvell,armada-8k-rtc";
160 reg = <0x284000 0x20>, <0x284080 0x24>;
161 reg-names = "rtc", "rtc-soc";
162 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
165 CP110_LABEL(thermal): thermal@400078 {
166 compatible = "marvell,armada-cp110-thermal";
167 reg = <0x400078 0x4>,
171 CP110_LABEL(syscon0): system-controller@440000 {
172 compatible = "syscon", "simple-mfd";
173 reg = <0x440000 0x2000>;
175 CP110_LABEL(clk): clock {
176 compatible = "marvell,cp110-clock";
180 CP110_LABEL(gpio1): gpio@100 {
181 compatible = "marvell,armada-8k-gpio";
186 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
187 interrupt-controller;
188 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
189 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
190 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
191 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
195 CP110_LABEL(gpio2): gpio@140 {
196 compatible = "marvell,armada-8k-gpio";
201 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
202 interrupt-controller;
203 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
204 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
205 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
206 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
211 CP110_LABEL(usb3_0): usb3@500000 {
212 compatible = "marvell,armada-8k-xhci",
214 reg = <0x500000 0x4000>;
216 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
217 clock-names = "core", "reg";
218 clocks = <&CP110_LABEL(clk) 1 22>,
219 <&CP110_LABEL(clk) 1 16>;
223 CP110_LABEL(usb3_1): usb3@510000 {
224 compatible = "marvell,armada-8k-xhci",
226 reg = <0x510000 0x4000>;
228 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
229 clock-names = "core", "reg";
230 clocks = <&CP110_LABEL(clk) 1 23>,
231 <&CP110_LABEL(clk) 1 16>;
235 CP110_LABEL(sata0): sata@540000 {
236 compatible = "marvell,armada-8k-ahci",
238 reg = <0x540000 0x30000>;
240 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&CP110_LABEL(clk) 1 15>,
242 <&CP110_LABEL(clk) 1 16>;
246 CP110_LABEL(xor0): xor@6a0000 {
247 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
248 reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
250 msi-parent = <&gic_v2m0>;
251 clock-names = "core", "reg";
252 clocks = <&CP110_LABEL(clk) 1 8>,
253 <&CP110_LABEL(clk) 1 14>;
256 CP110_LABEL(xor1): xor@6c0000 {
257 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
258 reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
260 msi-parent = <&gic_v2m0>;
261 clock-names = "core", "reg";
262 clocks = <&CP110_LABEL(clk) 1 7>,
263 <&CP110_LABEL(clk) 1 14>;
266 CP110_LABEL(spi0): spi@700600 {
267 compatible = "marvell,armada-380-spi";
268 reg = <0x700600 0x50>;
269 #address-cells = <0x1>;
271 clock-names = "core", "axi";
272 clocks = <&CP110_LABEL(clk) 1 21>,
273 <&CP110_LABEL(clk) 1 17>;
277 CP110_LABEL(spi1): spi@700680 {
278 compatible = "marvell,armada-380-spi";
279 reg = <0x700680 0x50>;
280 #address-cells = <1>;
282 clock-names = "core", "axi";
283 clocks = <&CP110_LABEL(clk) 1 21>,
284 <&CP110_LABEL(clk) 1 17>;
288 CP110_LABEL(i2c0): i2c@701000 {
289 compatible = "marvell,mv78230-i2c";
290 reg = <0x701000 0x20>;
291 #address-cells = <1>;
293 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
294 clock-names = "core", "reg";
295 clocks = <&CP110_LABEL(clk) 1 21>,
296 <&CP110_LABEL(clk) 1 17>;
300 CP110_LABEL(i2c1): i2c@701100 {
301 compatible = "marvell,mv78230-i2c";
302 reg = <0x701100 0x20>;
303 #address-cells = <1>;
305 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
306 clock-names = "core", "reg";
307 clocks = <&CP110_LABEL(clk) 1 21>,
308 <&CP110_LABEL(clk) 1 17>;
312 CP110_LABEL(uart0): serial@702000 {
313 compatible = "snps,dw-apb-uart";
314 reg = <0x702000 0x100>;
316 interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
318 clock-names = "baudclk", "apb_pclk";
319 clocks = <&CP110_LABEL(clk) 1 21>,
320 <&CP110_LABEL(clk) 1 17>;
324 CP110_LABEL(uart1): serial@702100 {
325 compatible = "snps,dw-apb-uart";
326 reg = <0x702100 0x100>;
328 interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
330 clock-names = "baudclk", "apb_pclk";
331 clocks = <&CP110_LABEL(clk) 1 21>,
332 <&CP110_LABEL(clk) 1 17>;
336 CP110_LABEL(uart2): serial@702200 {
337 compatible = "snps,dw-apb-uart";
338 reg = <0x702200 0x100>;
340 interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
342 clock-names = "baudclk", "apb_pclk";
343 clocks = <&CP110_LABEL(clk) 1 21>,
344 <&CP110_LABEL(clk) 1 17>;
348 CP110_LABEL(uart3): serial@702300 {
349 compatible = "snps,dw-apb-uart";
350 reg = <0x702300 0x100>;
352 interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
354 clock-names = "baudclk", "apb_pclk";
355 clocks = <&CP110_LABEL(clk) 1 21>,
356 <&CP110_LABEL(clk) 1 17>;
360 CP110_LABEL(nand_controller): nand@720000 {
362 * Due to the limitation of the pins available
363 * this controller is only usable on the CPM
364 * for A7K and on the CPS for A8K.
366 compatible = "marvell,armada-8k-nand-controller",
367 "marvell,armada370-nand-controller";
368 reg = <0x720000 0x54>;
369 #address-cells = <1>;
371 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
372 clock-names = "core", "reg";
373 clocks = <&CP110_LABEL(clk) 1 2>,
374 <&CP110_LABEL(clk) 1 17>;
375 marvell,system-controller = <&CP110_LABEL(syscon0)>;
379 CP110_LABEL(trng): trng@760000 {
380 compatible = "marvell,armada-8k-rng",
381 "inside-secure,safexcel-eip76";
382 reg = <0x760000 0x7d>;
383 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
384 clock-names = "core", "reg";
385 clocks = <&CP110_LABEL(clk) 1 25>,
386 <&CP110_LABEL(clk) 1 17>;
390 CP110_LABEL(sdhci0): sdhci@780000 {
391 compatible = "marvell,armada-cp110-sdhci";
392 reg = <0x780000 0x300>;
393 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
394 clock-names = "core", "axi";
395 clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
400 CP110_LABEL(crypto): crypto@800000 {
401 compatible = "inside-secure,safexcel-eip197b";
402 reg = <0x800000 0x200000>;
403 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
404 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
405 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
406 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
407 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
408 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
409 interrupt-names = "mem", "ring0", "ring1",
410 "ring2", "ring3", "eip";
411 clock-names = "core", "reg";
412 clocks = <&CP110_LABEL(clk) 1 26>,
413 <&CP110_LABEL(clk) 1 17>;
418 CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
419 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
420 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
421 <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
422 reg-names = "ctrl", "config";
423 #address-cells = <3>;
425 #interrupt-cells = <1>;
428 msi-parent = <&gic_v2m0>;
430 bus-range = <0 0xff>;
433 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000
434 /* non-prefetchable memory */
435 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
436 interrupt-map-mask = <0 0 0 0>;
437 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
438 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
440 clock-names = "core", "reg";
441 clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
445 CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
446 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
447 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
448 <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
449 reg-names = "ctrl", "config";
450 #address-cells = <3>;
452 #interrupt-cells = <1>;
455 msi-parent = <&gic_v2m0>;
457 bus-range = <0 0xff>;
460 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000
461 /* non-prefetchable memory */
462 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
463 interrupt-map-mask = <0 0 0 0>;
464 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
465 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
468 clock-names = "core", "reg";
469 clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
473 CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
474 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
475 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
476 <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
477 reg-names = "ctrl", "config";
478 #address-cells = <3>;
480 #interrupt-cells = <1>;
483 msi-parent = <&gic_v2m0>;
485 bus-range = <0 0xff>;
488 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000
489 /* non-prefetchable memory */
490 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
491 interrupt-map-mask = <0 0 0 0>;
492 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
493 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
496 clock-names = "core", "reg";
497 clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;