arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi

   1 /*
   2  * Copyright (C) 2016 Marvell Technology Group Ltd.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPLv2 or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 /*
  44  * Device Tree file for Marvell Armada CP110 Slave.
  45  */
  46
  47 #define ICU_GRP_NSR 0x0
  48
  49 / {
  50         cp110-slave {
  51                 #address-cells = <2>;
  52                 #size-cells = <2>;
  53                 compatible = "simple-bus";
  54                 interrupt-parent = <&cps_icu>;
  55                 ranges;
  56
  57                 config-space@f4000000 {
  58                         #address-cells = <1>;
  59                         #size-cells = <1>;
  60                         compatible = "simple-bus";
  61                         ranges = <0x0 0x0 0xf4000000 0x2000000>;
  62
  63                         cps_ethernet: ethernet@0 {
  64                                 compatible = "marvell,armada-7k-pp22";
  65                                 reg = <0x0 0x100000>, <0x129000 0xb000>;
  66                                 clocks = <&cps_clk 1 3>, <&cps_clk 1 9>,
  67                                          <&cps_clk 1 5>, <&cps_clk 1 18>;
  68                                 clock-names = "pp_clk", "gop_clk",
  69                                               "mg_clk", "axi_clk";
  70                                 marvell,system-controller = <&cps_syscon0>;
  71                                 status = "disabled";
  72                                 dma-coherent;
  73
  74                                 cps_eth0: eth0 {
  75                                         interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
  76                                                      <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
  77                                                      <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
  78                                                      <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
  79                                                      <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
  80                                         interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
  81                                                           "tx-cpu3", "rx-shared";
  82                                         port-id = <0>;
  83                                         gop-port-id = <0>;
  84                                         status = "disabled";
  85                                 };
  86
  87                                 cps_eth1: eth1 {
  88                                         interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
  89                                                      <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
  90                                                      <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
  91                                                      <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
  92                                                      <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
  93                                         interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
  94                                                           "tx-cpu3", "rx-shared";
  95                                         port-id = <1>;
  96                                         gop-port-id = <2>;
  97                                         status = "disabled";
  98                                 };
  99
 100                                 cps_eth2: eth2 {
 101                                         interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
 102                                                      <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
 103                                                      <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
 104                                                      <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
 105                                                      <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
 106                                         interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
 107                                                           "tx-cpu3", "rx-shared";
 108                                         port-id = <2>;
 109                                         gop-port-id = <3>;
 110                                         status = "disabled";
 111                                 };
 112                         };
 113
 114                         cps_comphy: phy@120000 {
 115                                 compatible = "marvell,comphy-cp110";
 116                                 reg = <0x120000 0x6000>;
 117                                 marvell,system-controller = <&cps_syscon0>;
 118                                 #address-cells = <1>;
 119                                 #size-cells = <0>;
 120
 121                                 cps_comphy0: phy@0 {
 122                                         reg = <0>;
 123                                         #phy-cells = <1>;
 124                                 };
 125
 126                                 cps_comphy1: phy@1 {
 127                                         reg = <1>;
 128                                         #phy-cells = <1>;
 129                                 };
 130
 131                                 cps_comphy2: phy@2 {
 132                                         reg = <2>;
 133                                         #phy-cells = <1>;
 134                                 };
 135
 136                                 cps_comphy3: phy@3 {
 137                                         reg = <3>;
 138                                         #phy-cells = <1>;
 139                                 };
 140
 141                                 cps_comphy4: phy@4 {
 142                                         reg = <4>;
 143                                         #phy-cells = <1>;
 144                                 };
 145
 146                                 cps_comphy5: phy@5 {
 147                                         reg = <5>;
 148                                         #phy-cells = <1>;
 149                                 };
 150                         };
 151
 152                         cps_mdio: mdio@12a200 {
 153                                 #address-cells = <1>;
 154                                 #size-cells = <0>;
 155                                 compatible = "marvell,orion-mdio";
 156                                 reg = <0x12a200 0x10>;
 157                                 clocks = <&cps_clk 1 9>, <&cps_clk 1 5>,
 158                                          <&cps_clk 1 6>, <&cps_clk 1 18>;
 159                                 status = "disabled";
 160                         };
 161
 162                         cps_xmdio: mdio@12a600 {
 163                                 #address-cells = <1>;
 164                                 #size-cells = <0>;
 165                                 compatible = "marvell,xmdio";
 166                                 reg = <0x12a600 0x10>;
 167                                 status = "disabled";
 168                         };
 169
 170                         cps_icu: interrupt-controller@1e0000 {
 171                                 compatible = "marvell,cp110-icu";
 172                                 reg = <0x1e0000 0x10>;
 173                                 #interrupt-cells = <3>;
 174                                 interrupt-controller;
 175                                 msi-parent = <&gicp>;
 176                         };
 177
 178                         cps_rtc: rtc@284000 {
 179                                 compatible = "marvell,armada-8k-rtc";
 180                                 reg = <0x284000 0x20>, <0x284080 0x24>;
 181                                 reg-names = "rtc", "rtc-soc";
 182                                 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
 183                         };
 184
 185                         cps_syscon0: system-controller@440000 {
 186                                 compatible = "syscon", "simple-mfd";
 187                                 reg = <0x440000 0x1000>;
 188
 189                                 cps_clk: clock {
 190                                         compatible = "marvell,cp110-clock";
 191                                         #clock-cells = <2>;
 192                                 };
 193
 194                                 cps_gpio1: gpio@100 {
 195                                         compatible = "marvell,armada-8k-gpio";
 196                                         offset = <0x100>;
 197                                         ngpios = <32>;
 198                                         gpio-controller;
 199                                         #gpio-cells = <2>;
 200                                         gpio-ranges = <&cps_pinctrl 0 0 32>;
 201                                         interrupt-controller;
 202                                         interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
 203                                                      <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
 204                                                      <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
 205                                                      <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
 206                                         status = "disabled";
 207                                 };
 208
 209                                 cps_gpio2: gpio@140 {
 210                                         compatible = "marvell,armada-8k-gpio";
 211                                         offset = <0x140>;
 212                                         ngpios = <31>;
 213                                         gpio-controller;
 214                                         #gpio-cells = <2>;
 215                                         gpio-ranges = <&cps_pinctrl 0 32 31>;
 216                                         interrupt-controller;
 217                                         interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
 218                                                      <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
 219                                                      <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
 220                                                      <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
 221                                         status = "disabled";
 222                                 };
 223
 224                         };
 225
 226                         cps_usb3_0: usb3@500000 {
 227                                 compatible = "marvell,armada-8k-xhci",
 228                                              "generic-xhci";
 229                                 reg = <0x500000 0x4000>;
 230                                 dma-coherent;
 231                                 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
 232                                 clocks = <&cps_clk 1 22>;
 233                                 status = "disabled";
 234                         };
 235
 236                         cps_usb3_1: usb3@510000 {
 237                                 compatible = "marvell,armada-8k-xhci",
 238                                              "generic-xhci";
 239                                 reg = <0x510000 0x4000>;
 240                                 dma-coherent;
 241                                 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
 242                                 clocks = <&cps_clk 1 23>;
 243                                 status = "disabled";
 244                         };
 245
 246                         cps_sata0: sata@540000 {
 247                                 compatible = "marvell,armada-8k-ahci",
 248                                              "generic-ahci";
 249                                 reg = <0x540000 0x30000>;
 250                                 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
 251                                 clocks = <&cps_clk 1 15>;
 252                                 status = "disabled";
 253                         };
 254
 255                         cps_xor0: xor@6a0000 {
 256                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 257                                 reg = <0x6a0000 0x1000>,
 258                                       <0x6b0000 0x1000>;
 259                                 dma-coherent;
 260                                 msi-parent = <&gic_v2m0>;
 261                                 clocks = <&cps_clk 1 8>;
 262                         };
 263
 264                         cps_xor1: xor@6c0000 {
 265                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 266                                 reg = <0x6c0000 0x1000>,
 267                                       <0x6d0000 0x1000>;
 268                                 dma-coherent;
 269                                 msi-parent = <&gic_v2m0>;
 270                                 clocks = <&cps_clk 1 7>;
 271                         };
 272
 273                         cps_spi0: spi@700600 {
 274                                 compatible = "marvell,armada-380-spi";
 275                                 reg = <0x700600 0x50>;
 276                                 #address-cells = <0x1>;
 277                                 #size-cells = <0x0>;
 278                                 cell-index = <3>;
 279                                 clocks = <&cps_clk 1 21>;
 280                                 status = "disabled";
 281                         };
 282
 283                         cps_spi1: spi@700680 {
 284                                 compatible = "marvell,armada-380-spi";
 285                                 reg = <0x700680 0x50>;
 286                                 #address-cells = <1>;
 287                                 #size-cells = <0>;
 288                                 cell-index = <4>;
 289                                 clocks = <&cps_clk 1 21>;
 290                                 status = "disabled";
 291                         };
 292
 293                         cps_i2c0: i2c@701000 {
 294                                 compatible = "marvell,mv78230-i2c";
 295                                 reg = <0x701000 0x20>;
 296                                 #address-cells = <1>;
 297                                 #size-cells = <0>;
 298                                 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
 299                                 clocks = <&cps_clk 1 21>;
 300                                 status = "disabled";
 301                         };
 302
 303                         cps_i2c1: i2c@701100 {
 304                                 compatible = "marvell,mv78230-i2c";
 305                                 reg = <0x701100 0x20>;
 306                                 #address-cells = <1>;
 307                                 #size-cells = <0>;
 308                                 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
 309                                 clocks = <&cps_clk 1 21>;
 310                                 status = "disabled";
 311                         };
 312
 313                         cps_nand: nand@720000 {
 314                                 /*
 315                                  * Due to the limiation of the pin available
 316                                  * this controller is only usable on the CPM
 317                                  * for A7K and on the CPS for A8K.
 318                                  */
 319                                 compatible = "marvell,armada370-nand";
 320                                 reg = <0x720000 0x54>;
 321                                 #address-cells = <1>;
 322                                 #size-cells = <1>;
 323                                 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
 324                                 clocks = <&cps_clk 1 2>;
 325                                 status = "disabled";
 326                         };
 327
 328                         cps_trng: trng@760000 {
 329                                 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
 330                                 reg = <0x760000 0x7d>;
 331                                 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
 332                                 clocks = <&cps_clk 1 25>;
 333                                 status = "okay";
 334                         };
 335
 336                         cps_crypto: crypto@800000 {
 337                                 compatible = "inside-secure,safexcel-eip197";
 338                                 reg = <0x800000 0x200000>;
 339                                 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
 340                                              <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
 341                                              <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
 342                                              <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
 343                                              <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
 344                                              <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
 345                                 interrupt-names = "mem", "ring0", "ring1",
 346                                                   "ring2", "ring3", "eip";
 347                                 clocks = <&cps_clk 1 26>;
 348                                 dma-coherent;
 349                                 /*
 350                                  * The cryptographic engine found on the cp110
 351                                  * master is enabled by default at the SoC
 352                                  * level. Because it is not possible as of now
 353                                  * to enable two cryptographic engines in
 354                                  * parallel, disable this one by default.
 355                                  */
 356                                 status = "disabled";
 357                         };
 358                 };
 359
 360                 cps_pcie0: pcie@f4600000 {
 361                         compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
 362                         reg = <0 0xf4600000 0 0x10000>,
 363                               <0 0xfaf00000 0 0x80000>;
 364                         reg-names = "ctrl", "config";
 365                         #address-cells = <3>;
 366                         #size-cells = <2>;
 367                         #interrupt-cells = <1>;
 368                         device_type = "pci";
 369                         dma-coherent;
 370                         msi-parent = <&gic_v2m0>;
 371
 372                         bus-range = <0 0xff>;
 373                         ranges =
 374                                 /* downstream I/O */
 375                                 <0x81000000 0 0xfd000000 0  0xfd000000 0 0x10000
 376                                 /* non-prefetchable memory */
 377                                 0x82000000 0 0xfa000000 0  0xfa000000 0 0xf00000>;
 378                         interrupt-map-mask = <0 0 0 0>;
 379                         interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
 380                         interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
 381                         num-lanes = <1>;
 382                         clocks = <&cps_clk 1 13>;
 383                         status = "disabled";
 384                 };
 385
 386                 cps_pcie1: pcie@f4620000 {
 387                         compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
 388                         reg = <0 0xf4620000 0 0x10000>,
 389                               <0 0xfbf00000 0 0x80000>;
 390                         reg-names = "ctrl", "config";
 391                         #address-cells = <3>;
 392                         #size-cells = <2>;
 393                         #interrupt-cells = <1>;
 394                         device_type = "pci";
 395                         dma-coherent;
 396                         msi-parent = <&gic_v2m0>;
 397
 398                         bus-range = <0 0xff>;
 399                         ranges =
 400                                 /* downstream I/O */
 401                                 <0x81000000 0 0xfd010000 0  0xfd010000 0 0x10000
 402                                 /* non-prefetchable memory */
 403                                 0x82000000 0 0xfb000000 0  0xfb000000 0 0xf00000>;
 404                         interrupt-map-mask = <0 0 0 0>;
 405                         interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
 406                         interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
 407
 408                         num-lanes = <1>;
 409                         clocks = <&cps_clk 1 11>;
 410                         status = "disabled";
 411                 };
 412
 413                 cps_pcie2: pcie@f4640000 {
 414                         compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
 415                         reg = <0 0xf4640000 0 0x10000>,
 416                               <0 0xfcf00000 0 0x80000>;
 417                         reg-names = "ctrl", "config";
 418                         #address-cells = <3>;
 419                         #size-cells = <2>;
 420                         #interrupt-cells = <1>;
 421                         device_type = "pci";
 422                         dma-coherent;
 423                         msi-parent = <&gic_v2m0>;
 424
 425                         bus-range = <0 0xff>;
 426                         ranges =
 427                                 /* downstream I/O */
 428                                 <0x81000000 0 0xfd020000 0  0xfd020000 0 0x10000
 429                                 /* non-prefetchable memory */
 430                                 0x82000000 0 0xfc000000 0  0xfc000000 0 0xf00000>;
 431                         interrupt-map-mask = <0 0 0 0>;
 432                         interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
 433                         interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
 434
 435                         num-lanes = <1>;
 436                         clocks = <&cps_clk 1 12>;
 437                         status = "disabled";
 438                 };
 439         };
 440 };