1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2019 Marvell Technology Group Ltd.
5 * Device Tree file for Marvell Armada AP80x.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
25 compatible = "arm,psci-0.2";
35 * This area matches the mapping done with a
36 * mainline U-Boot, and should be updated by the
41 reg = <0x0 0x4000000 0x0 0x200000>;
46 reg = <0 0x4400000 0 0x1000000>;
54 compatible = "simple-bus";
55 interrupt-parent = <&gic>;
58 config-space@f0000000 {
61 compatible = "simple-bus";
62 ranges = <0x0 0x0 0xf0000000 0x1000000>;
65 compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
66 reg = <0x100000 0x100000>;
69 #global-interrupts = <1>;
70 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
82 gic: interrupt-controller@210000 {
83 compatible = "arm,gic-400";
84 #interrupt-cells = <3>;
89 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
90 reg = <0x210000 0x10000>,
95 gic_v2m0: v2m@280000 {
96 compatible = "arm,gic-v2m-frame";
98 reg = <0x280000 0x1000>;
99 arm,msi-base-spi = <160>;
100 arm,msi-num-spis = <32>;
102 gic_v2m1: v2m@290000 {
103 compatible = "arm,gic-v2m-frame";
105 reg = <0x290000 0x1000>;
106 arm,msi-base-spi = <192>;
107 arm,msi-num-spis = <32>;
109 gic_v2m2: v2m@2a0000 {
110 compatible = "arm,gic-v2m-frame";
112 reg = <0x2a0000 0x1000>;
113 arm,msi-base-spi = <224>;
114 arm,msi-num-spis = <32>;
116 gic_v2m3: v2m@2b0000 {
117 compatible = "arm,gic-v2m-frame";
119 reg = <0x2b0000 0x1000>;
120 arm,msi-base-spi = <256>;
121 arm,msi-num-spis = <32>;
126 compatible = "arm,armv8-timer";
127 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
128 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
129 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
130 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
134 compatible = "arm,cortex-a72-pmu";
135 interrupt-parent = <&pic>;
140 compatible = "marvell,odmi-controller";
141 interrupt-controller;
143 marvell,odmi-frames = <4>;
144 reg = <0x300000 0x4000>,
148 marvell,spi-base = <128>, <136>, <144>, <152>;
152 compatible = "marvell,ap806-gicp";
153 reg = <0x3f0040 0x10>;
154 marvell,spi-ranges = <64 64>, <288 64>;
158 pic: interrupt-controller@3f0100 {
159 compatible = "marvell,armada-8k-pic";
160 reg = <0x3f0100 0x10>;
161 #interrupt-cells = <1>;
162 interrupt-controller;
163 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
166 sei: interrupt-controller@3f0200 {
167 compatible = "marvell,ap806-sei";
168 reg = <0x3f0200 0x40>;
169 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
170 #interrupt-cells = <1>;
171 interrupt-controller;
176 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
177 reg = <0x400000 0x1000>,
179 msi-parent = <&gic_v2m0>;
180 clocks = <&ap_clk 3>;
185 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
186 reg = <0x420000 0x1000>,
188 msi-parent = <&gic_v2m0>;
189 clocks = <&ap_clk 3>;
194 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
195 reg = <0x440000 0x1000>,
197 msi-parent = <&gic_v2m0>;
198 clocks = <&ap_clk 3>;
203 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
204 reg = <0x460000 0x1000>,
206 msi-parent = <&gic_v2m0>;
207 clocks = <&ap_clk 3>;
212 compatible = "marvell,armada-380-spi";
213 reg = <0x510600 0x50>;
214 #address-cells = <1>;
216 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&ap_clk 3>;
222 compatible = "marvell,mv78230-i2c";
223 reg = <0x511000 0x20>;
224 #address-cells = <1>;
226 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&ap_clk 3>;
231 uart0: serial@512000 {
232 compatible = "snps,dw-apb-uart";
233 reg = <0x512000 0x100>;
235 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&ap_clk 3>;
241 uart1: serial@512100 {
242 compatible = "snps,dw-apb-uart";
243 reg = <0x512100 0x100>;
245 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&ap_clk 3>;
252 watchdog: watchdog@610000 {
253 compatible = "arm,sbsa-gwdt";
254 reg = <0x610000 0x1000>, <0x600000 0x1000>;
255 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
258 ap_sdhci0: mmc@6e0000 {
259 compatible = "marvell,armada-ap806-sdhci";
260 reg = <0x6e0000 0x300>;
261 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
262 clock-names = "core";
263 clocks = <&ap_clk 4>;
265 marvell,xenon-phy-slow-mode;
269 ap_syscon0: system-controller@6f4000 {
270 compatible = "syscon", "simple-mfd";
271 reg = <0x6f4000 0x2000>;
273 ap_pinctrl: pinctrl {
274 compatible = "marvell,ap806-pinctrl";
276 uart0_pins: uart0-pins {
277 marvell,pins = "mpp11", "mpp19";
278 marvell,function = "uart0";
283 compatible = "marvell,armada-8k-gpio";
288 gpio-ranges = <&ap_pinctrl 0 0 20>;
289 marvell,pwm-offset = <0x10c0>;
291 clocks = <&ap_clk 3>;
295 ap_syscon1: system-controller@6f8000 {
296 compatible = "syscon", "simple-mfd";
297 reg = <0x6f8000 0x1000>;
298 #address-cells = <1>;
301 ap_thermal: thermal-sensor@80 {
302 compatible = "marvell,armada-ap806-thermal";
304 interrupt-parent = <&sei>;
306 #thermal-sensor-cells = <1>;
313 * The thermal IP features one internal sensor plus, if applicable, one
314 * remote channel wired to one sensor per CPU.
316 * Only one thermal zone per AP/CP may trigger interrupts at a time, the
317 * first one that will have a critical trip point will be chosen.
320 ap_thermal_ic: ap-ic-thermal {
321 polling-delay-passive = <0>; /* Interrupt driven */
322 polling-delay = <0>; /* Interrupt driven */
324 thermal-sensors = <&ap_thermal 0>;
328 temperature = <100000>; /* mC degrees */
329 hysteresis = <2000>; /* mC degrees */
337 ap_thermal_cpu0: ap-cpu0-thermal {
338 polling-delay-passive = <1000>;
339 polling-delay = <1000>;
341 thermal-sensors = <&ap_thermal 1>;
345 temperature = <85000>;
349 cpu0_emerg: cpu0-emerg {
350 temperature = <95000>;
359 cooling-device = <&cpu0 1 2>,
362 map0_emerg: map0-ermerg {
363 trip = <&cpu0_emerg>;
364 cooling-device = <&cpu0 3 3>,
370 ap_thermal_cpu1: ap-cpu1-thermal {
371 polling-delay-passive = <1000>;
372 polling-delay = <1000>;
374 thermal-sensors = <&ap_thermal 2>;
378 temperature = <85000>;
382 cpu1_emerg: cpu1-emerg {
383 temperature = <95000>;
392 cooling-device = <&cpu0 1 2>,
395 map1_emerg: map1-emerg {
396 trip = <&cpu1_emerg>;
397 cooling-device = <&cpu0 3 3>,
403 ap_thermal_cpu2: ap-cpu2-thermal {
404 polling-delay-passive = <1000>;
405 polling-delay = <1000>;
407 thermal-sensors = <&ap_thermal 3>;
411 temperature = <85000>;
415 cpu2_emerg: cpu2-emerg {
416 temperature = <95000>;
425 cooling-device = <&cpu2 1 2>,
428 map2_emerg: map2-emerg {
429 trip = <&cpu2_emerg>;
430 cooling-device = <&cpu2 3 3>,
436 ap_thermal_cpu3: ap-cpu3-thermal {
437 polling-delay-passive = <1000>;
438 polling-delay = <1000>;
440 thermal-sensors = <&ap_thermal 4>;
444 temperature = <85000>;
448 cpu3_emerg: cpu3-emerg {
449 temperature = <95000>;
456 map3_hot: map3-bhot {
458 cooling-device = <&cpu2 1 2>,
461 map3_emerg: map3-emerg {
462 trip = <&cpu3_emerg>;
463 cooling-device = <&cpu2 3 3>,