arch/arm64/boot/dts/marvell/armada-ap80x.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2019 Marvell Technology Group Ltd.
   4  *
   5  * Device Tree file for Marvell Armada AP80x.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10
  11 /dts-v1/;
  12
  13 / {
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         aliases {
  18                 serial0 = &uart0;
  19                 serial1 = &uart1;
  20                 gpio0 = &ap_gpio;
  21                 spi0 = &spi0;
  22         };
  23
  24         psci {
  25                 compatible = "arm,psci-0.2";
  26                 method = "smc";
  27         };
  28
  29         reserved-memory {
  30                 #address-cells = <2>;
  31                 #size-cells = <2>;
  32                 ranges;
  33
  34                 /*
  35                  * This area matches the mapping done with a
  36                  * mainline U-Boot, and should be updated by the
  37                  * bootloader.
  38                  */
  39
  40                 psci-area@4000000 {
  41                         reg = <0x0 0x4000000 0x0 0x200000>;
  42                         no-map;
  43                 };
  44         };
  45
  46         AP_NAME {
  47                 #address-cells = <2>;
  48                 #size-cells = <2>;
  49                 compatible = "simple-bus";
  50                 interrupt-parent = <&gic>;
  51                 ranges;
  52
  53                 config-space@f0000000 {
  54                         #address-cells = <1>;
  55                         #size-cells = <1>;
  56                         compatible = "simple-bus";
  57                         ranges = <0x0 0x0 0xf0000000 0x1000000>;
  58
  59                         smmu: iommu@5000000 {
  60                                 compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
  61                                 reg = <0x100000 0x100000>;
  62                                 dma-coherent;
  63                                 #iommu-cells = <1>;
  64                                 #global-interrupts = <1>;
  65                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  66                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  67                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  68                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  69                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  70                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  71                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  72                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  73                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  74                                 status = "disabled";
  75                         };
  76
  77                         gic: interrupt-controller@210000 {
  78                                 compatible = "arm,gic-400";
  79                                 #interrupt-cells = <3>;
  80                                 #address-cells = <1>;
  81                                 #size-cells = <1>;
  82                                 ranges;
  83                                 interrupt-controller;
  84                                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  85                                 reg = <0x210000 0x10000>,
  86                                       <0x220000 0x20000>,
  87                                       <0x240000 0x20000>,
  88                                       <0x260000 0x20000>;
  89
  90                                 gic_v2m0: v2m@280000 {
  91                                         compatible = "arm,gic-v2m-frame";
  92                                         msi-controller;
  93                                         reg = <0x280000 0x1000>;
  94                                         arm,msi-base-spi = <160>;
  95                                         arm,msi-num-spis = <32>;
  96                                 };
  97                                 gic_v2m1: v2m@290000 {
  98                                         compatible = "arm,gic-v2m-frame";
  99                                         msi-controller;
 100                                         reg = <0x290000 0x1000>;
 101                                         arm,msi-base-spi = <192>;
 102                                         arm,msi-num-spis = <32>;
 103                                 };
 104                                 gic_v2m2: v2m@2a0000 {
 105                                         compatible = "arm,gic-v2m-frame";
 106                                         msi-controller;
 107                                         reg = <0x2a0000 0x1000>;
 108                                         arm,msi-base-spi = <224>;
 109                                         arm,msi-num-spis = <32>;
 110                                 };
 111                                 gic_v2m3: v2m@2b0000 {
 112                                         compatible = "arm,gic-v2m-frame";
 113                                         msi-controller;
 114                                         reg = <0x2b0000 0x1000>;
 115                                         arm,msi-base-spi = <256>;
 116                                         arm,msi-num-spis = <32>;
 117                                 };
 118                         };
 119
 120                         timer {
 121                                 compatible = "arm,armv8-timer";
 122                                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 123                                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 124                                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 125                                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 126                         };
 127
 128                         pmu {
 129                                 compatible = "arm,cortex-a72-pmu";
 130                                 interrupt-parent = <&pic>;
 131                                 interrupts = <17>;
 132                         };
 133
 134                         odmi: odmi@300000 {
 135                                 compatible = "marvell,odmi-controller";
 136                                 msi-controller;
 137                                 marvell,odmi-frames = <4>;
 138                                 reg = <0x300000 0x4000>,
 139                                       <0x304000 0x4000>,
 140                                       <0x308000 0x4000>,
 141                                       <0x30C000 0x4000>;
 142                                 marvell,spi-base = <128>, <136>, <144>, <152>;
 143                         };
 144
 145                         gicp: gicp@3f0040 {
 146                                 compatible = "marvell,ap806-gicp";
 147                                 reg = <0x3f0040 0x10>;
 148                                 marvell,spi-ranges = <64 64>, <288 64>;
 149                                 msi-controller;
 150                         };
 151
 152                         pic: interrupt-controller@3f0100 {
 153                                 compatible = "marvell,armada-8k-pic";
 154                                 reg = <0x3f0100 0x10>;
 155                                 #interrupt-cells = <1>;
 156                                 interrupt-controller;
 157                                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
 158                         };
 159
 160                         sei: interrupt-controller@3f0200 {
 161                                 compatible = "marvell,ap806-sei";
 162                                 reg = <0x3f0200 0x40>;
 163                                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 164                                 #interrupt-cells = <1>;
 165                                 interrupt-controller;
 166                                 msi-controller;
 167                         };
 168
 169                         xor@400000 {
 170                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 171                                 reg = <0x400000 0x1000>,
 172                                       <0x410000 0x1000>;
 173                                 msi-parent = <&gic_v2m0>;
 174                                 clocks = <&ap_clk 3>;
 175                                 dma-coherent;
 176                         };
 177
 178                         xor@420000 {
 179                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 180                                 reg = <0x420000 0x1000>,
 181                                       <0x430000 0x1000>;
 182                                 msi-parent = <&gic_v2m0>;
 183                                 clocks = <&ap_clk 3>;
 184                                 dma-coherent;
 185                         };
 186
 187                         xor@440000 {
 188                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 189                                 reg = <0x440000 0x1000>,
 190                                       <0x450000 0x1000>;
 191                                 msi-parent = <&gic_v2m0>;
 192                                 clocks = <&ap_clk 3>;
 193                                 dma-coherent;
 194                         };
 195
 196                         xor@460000 {
 197                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 198                                 reg = <0x460000 0x1000>,
 199                                       <0x470000 0x1000>;
 200                                 msi-parent = <&gic_v2m0>;
 201                                 clocks = <&ap_clk 3>;
 202                                 dma-coherent;
 203                         };
 204
 205                         spi0: spi@510600 {
 206                                 compatible = "marvell,armada-380-spi";
 207                                 reg = <0x510600 0x50>;
 208                                 #address-cells = <1>;
 209                                 #size-cells = <0>;
 210                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 211                                 clocks = <&ap_clk 3>;
 212                                 status = "disabled";
 213                         };
 214
 215                         i2c0: i2c@511000 {
 216                                 compatible = "marvell,mv78230-i2c";
 217                                 reg = <0x511000 0x20>;
 218                                 #address-cells = <1>;
 219                                 #size-cells = <0>;
 220                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 221                                 clocks = <&ap_clk 3>;
 222                                 status = "disabled";
 223                         };
 224
 225                         uart0: serial@512000 {
 226                                 compatible = "snps,dw-apb-uart";
 227                                 reg = <0x512000 0x100>;
 228                                 reg-shift = <2>;
 229                                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 230                                 reg-io-width = <1>;
 231                                 clocks = <&ap_clk 3>;
 232                                 status = "disabled";
 233                         };
 234
 235                         uart1: serial@512100 {
 236                                 compatible = "snps,dw-apb-uart";
 237                                 reg = <0x512100 0x100>;
 238                                 reg-shift = <2>;
 239                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 240                                 reg-io-width = <1>;
 241                                 clocks = <&ap_clk 3>;
 242                                 status = "disabled";
 243
 244                         };
 245
 246                         watchdog: watchdog@610000 {
 247                                 compatible = "arm,sbsa-gwdt";
 248                                 reg = <0x610000 0x1000>, <0x600000 0x1000>;
 249                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 250                         };
 251
 252                         ap_sdhci0: mmc@6e0000 {
 253                                 compatible = "marvell,armada-ap806-sdhci";
 254                                 reg = <0x6e0000 0x300>;
 255                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 256                                 clock-names = "core";
 257                                 clocks = <&ap_clk 4>;
 258                                 dma-coherent;
 259                                 marvell,xenon-phy-slow-mode;
 260                                 status = "disabled";
 261                         };
 262
 263                         ap_syscon0: system-controller@6f4000 {
 264                                 compatible = "syscon", "simple-mfd";
 265                                 reg = <0x6f4000 0x2000>;
 266
 267                                 ap_pinctrl: pinctrl {
 268                                         compatible = "marvell,ap806-pinctrl";
 269
 270                                         uart0_pins: uart0-pins {
 271                                                 marvell,pins = "mpp11", "mpp19";
 272                                                 marvell,function = "uart0";
 273                                         };
 274                                 };
 275
 276                                 ap_gpio: gpio@1040 {
 277                                         compatible = "marvell,armada-8k-gpio";
 278                                         offset = <0x1040>;
 279                                         ngpios = <20>;
 280                                         gpio-controller;
 281                                         #gpio-cells = <2>;
 282                                         gpio-ranges = <&ap_pinctrl 0 0 20>;
 283                                         marvell,pwm-offset = <0x10c0>;
 284                                         #pwm-cells = <2>;
 285                                         clocks = <&ap_clk 3>;
 286                                 };
 287                         };
 288
 289                         ap_syscon1: system-controller@6f8000 {
 290                                 compatible = "syscon", "simple-mfd";
 291                                 reg = <0x6f8000 0x1000>;
 292                                 #address-cells = <1>;
 293                                 #size-cells = <1>;
 294
 295                                 ap_thermal: thermal-sensor@80 {
 296                                         compatible = "marvell,armada-ap806-thermal";
 297                                         reg = <0x80 0x10>;
 298                                         interrupt-parent = <&sei>;
 299                                         interrupts = <18>;
 300                                         #thermal-sensor-cells = <1>;
 301                                 };
 302                         };
 303                 };
 304         };
 305
 306         /*
 307          * The thermal IP features one internal sensor plus, if applicable, one
 308          * remote channel wired to one sensor per CPU.
 309          *
 310          * Only one thermal zone per AP/CP may trigger interrupts at a time, the
 311          * first one that will have a critical trip point will be chosen.
 312          */
 313         thermal-zones {
 314                 ap_thermal_ic: ap-thermal-ic {
 315                         polling-delay-passive = <0>; /* Interrupt driven */
 316                         polling-delay = <0>; /* Interrupt driven */
 317
 318                         thermal-sensors = <&ap_thermal 0>;
 319
 320                         trips {
 321                                 ap_crit: ap-crit {
 322                                         temperature = <100000>; /* mC degrees */
 323                                         hysteresis = <2000>; /* mC degrees */
 324                                         type = "critical";
 325                                 };
 326                         };
 327
 328                         cooling-maps { };
 329                 };
 330
 331                 ap_thermal_cpu0: ap-thermal-cpu0 {
 332                         polling-delay-passive = <1000>;
 333                         polling-delay = <1000>;
 334
 335                         thermal-sensors = <&ap_thermal 1>;
 336
 337                         trips {
 338                                 cpu0_hot: cpu0-hot {
 339                                         temperature = <85000>;
 340                                         hysteresis = <2000>;
 341                                         type = "passive";
 342                                 };
 343                                 cpu0_emerg: cpu0-emerg {
 344                                         temperature = <95000>;
 345                                         hysteresis = <2000>;
 346                                         type = "passive";
 347                                 };
 348                         };
 349
 350                         cooling-maps {
 351                                 map0_hot: map0-hot {
 352                                         trip = <&cpu0_hot>;
 353                                         cooling-device = <&cpu0 1 2>,
 354                                                 <&cpu1 1 2>;
 355                                 };
 356                                 map0_emerg: map0-ermerg {
 357                                         trip = <&cpu0_emerg>;
 358                                         cooling-device = <&cpu0 3 3>,
 359                                                 <&cpu1 3 3>;
 360                                 };
 361                         };
 362                 };
 363
 364                 ap_thermal_cpu1: ap-thermal-cpu1 {
 365                         polling-delay-passive = <1000>;
 366                         polling-delay = <1000>;
 367
 368                         thermal-sensors = <&ap_thermal 2>;
 369
 370                         trips {
 371                                 cpu1_hot: cpu1-hot {
 372                                         temperature = <85000>;
 373                                         hysteresis = <2000>;
 374                                         type = "passive";
 375                                 };
 376                                 cpu1_emerg: cpu1-emerg {
 377                                         temperature = <95000>;
 378                                         hysteresis = <2000>;
 379                                         type = "passive";
 380                                 };
 381                         };
 382
 383                         cooling-maps {
 384                                 map1_hot: map1-hot {
 385                                         trip = <&cpu1_hot>;
 386                                         cooling-device = <&cpu0 1 2>,
 387                                                 <&cpu1 1 2>;
 388                                 };
 389                                 map1_emerg: map1-emerg {
 390                                         trip = <&cpu1_emerg>;
 391                                         cooling-device = <&cpu0 3 3>,
 392                                                 <&cpu1 3 3>;
 393                                 };
 394                         };
 395                 };
 396
 397                 ap_thermal_cpu2: ap-thermal-cpu2 {
 398                         polling-delay-passive = <1000>;
 399                         polling-delay = <1000>;
 400
 401                         thermal-sensors = <&ap_thermal 3>;
 402
 403                         trips {
 404                                 cpu2_hot: cpu2-hot {
 405                                         temperature = <85000>;
 406                                         hysteresis = <2000>;
 407                                         type = "passive";
 408                                 };
 409                                 cpu2_emerg: cpu2-emerg {
 410                                         temperature = <95000>;
 411                                         hysteresis = <2000>;
 412                                         type = "passive";
 413                                 };
 414                         };
 415
 416                         cooling-maps {
 417                                 map2_hot: map2-hot {
 418                                         trip = <&cpu2_hot>;
 419                                         cooling-device = <&cpu2 1 2>,
 420                                                 <&cpu3 1 2>;
 421                                 };
 422                                 map2_emerg: map2-emerg {
 423                                         trip = <&cpu2_emerg>;
 424                                         cooling-device = <&cpu2 3 3>,
 425                                                 <&cpu3 3 3>;
 426                                 };
 427                         };
 428                 };
 429
 430                 ap_thermal_cpu3: ap-thermal-cpu3 {
 431                         polling-delay-passive = <1000>;
 432                         polling-delay = <1000>;
 433
 434                         thermal-sensors = <&ap_thermal 4>;
 435
 436                         trips {
 437                                 cpu3_hot: cpu3-hot {
 438                                         temperature = <85000>;
 439                                         hysteresis = <2000>;
 440                                         type = "passive";
 441                                 };
 442                                 cpu3_emerg: cpu3-emerg {
 443                                         temperature = <95000>;
 444                                         hysteresis = <2000>;
 445                                         type = "passive";
 446                                 };
 447                         };
 448
 449                         cooling-maps {
 450                                 map3_hot: map3-bhot {
 451                                         trip = <&cpu3_hot>;
 452                                         cooling-device = <&cpu2 1 2>,
 453                                                 <&cpu3 1 2>;
 454                                 };
 455                                 map3_emerg: map3-emerg {
 456                                         trip = <&cpu3_emerg>;
 457                                         cooling-device = <&cpu2 3 3>,
 458                                                 <&cpu3 3 3>;
 459                                 };
 460                         };
 461                 };
 462         };
 463 };