1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
5 * Device Tree file for Marvell Armada AP806.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
14 model = "Marvell Armada AP806";
15 compatible = "marvell,armada-ap806";
27 compatible = "arm,psci-0.2";
37 * This area matches the mapping done with a
38 * mainline U-Boot, and should be updated by the
43 reg = <0x0 0x4000000 0x0 0x200000>;
51 compatible = "simple-bus";
52 interrupt-parent = <&gic>;
55 config-space@f0000000 {
58 compatible = "simple-bus";
59 ranges = <0x0 0x0 0xf0000000 0x1000000>;
61 gic: interrupt-controller@210000 {
62 compatible = "arm,gic-400";
63 #interrupt-cells = <3>;
68 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
69 reg = <0x210000 0x10000>,
74 gic_v2m0: v2m@280000 {
75 compatible = "arm,gic-v2m-frame";
77 reg = <0x280000 0x1000>;
78 arm,msi-base-spi = <160>;
79 arm,msi-num-spis = <32>;
81 gic_v2m1: v2m@290000 {
82 compatible = "arm,gic-v2m-frame";
84 reg = <0x290000 0x1000>;
85 arm,msi-base-spi = <192>;
86 arm,msi-num-spis = <32>;
88 gic_v2m2: v2m@2a0000 {
89 compatible = "arm,gic-v2m-frame";
91 reg = <0x2a0000 0x1000>;
92 arm,msi-base-spi = <224>;
93 arm,msi-num-spis = <32>;
95 gic_v2m3: v2m@2b0000 {
96 compatible = "arm,gic-v2m-frame";
98 reg = <0x2b0000 0x1000>;
99 arm,msi-base-spi = <256>;
100 arm,msi-num-spis = <32>;
105 compatible = "arm,armv8-timer";
106 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
107 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
108 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
109 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
113 compatible = "arm,cortex-a72-pmu";
114 interrupt-parent = <&pic>;
119 compatible = "marvell,odmi-controller";
120 interrupt-controller;
122 marvell,odmi-frames = <4>;
123 reg = <0x300000 0x4000>,
127 marvell,spi-base = <128>, <136>, <144>, <152>;
131 compatible = "marvell,ap806-gicp";
132 reg = <0x3f0040 0x10>;
133 marvell,spi-ranges = <64 64>, <288 64>;
137 pic: interrupt-controller@3f0100 {
138 compatible = "marvell,armada-8k-pic";
139 reg = <0x3f0100 0x10>;
140 #interrupt-cells = <1>;
141 interrupt-controller;
142 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
145 sei: interrupt-controller@3f0200 {
146 compatible = "marvell,ap806-sei";
147 reg = <0x3f0200 0x40>;
148 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
149 #interrupt-cells = <1>;
150 interrupt-controller;
155 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
156 reg = <0x400000 0x1000>,
158 msi-parent = <&gic_v2m0>;
159 clocks = <&ap_clk 3>;
164 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
165 reg = <0x420000 0x1000>,
167 msi-parent = <&gic_v2m0>;
168 clocks = <&ap_clk 3>;
173 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
174 reg = <0x440000 0x1000>,
176 msi-parent = <&gic_v2m0>;
177 clocks = <&ap_clk 3>;
182 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
183 reg = <0x460000 0x1000>,
185 msi-parent = <&gic_v2m0>;
186 clocks = <&ap_clk 3>;
191 compatible = "marvell,armada-380-spi";
192 reg = <0x510600 0x50>;
193 #address-cells = <1>;
195 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&ap_clk 3>;
201 compatible = "marvell,mv78230-i2c";
202 reg = <0x511000 0x20>;
203 #address-cells = <1>;
205 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&ap_clk 3>;
211 uart0: serial@512000 {
212 compatible = "snps,dw-apb-uart";
213 reg = <0x512000 0x100>;
215 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&ap_clk 3>;
221 uart1: serial@512100 {
222 compatible = "snps,dw-apb-uart";
223 reg = <0x512100 0x100>;
225 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&ap_clk 3>;
232 watchdog: watchdog@610000 {
233 compatible = "arm,sbsa-gwdt";
234 reg = <0x610000 0x1000>, <0x600000 0x1000>;
235 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
238 ap_sdhci0: sdhci@6e0000 {
239 compatible = "marvell,armada-ap806-sdhci";
240 reg = <0x6e0000 0x300>;
241 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
242 clock-names = "core";
243 clocks = <&ap_clk 4>;
245 marvell,xenon-phy-slow-mode;
249 ap_syscon: system-controller@6f4000 {
250 compatible = "syscon", "simple-mfd";
251 reg = <0x6f4000 0x2000>;
254 compatible = "marvell,ap806-clock";
258 ap_pinctrl: pinctrl {
259 compatible = "marvell,ap806-pinctrl";
261 uart0_pins: uart0-pins {
262 marvell,pins = "mpp11", "mpp19";
263 marvell,function = "uart0";
268 compatible = "marvell,armada-8k-gpio";
273 gpio-ranges = <&ap_pinctrl 0 0 20>;
277 ap_syscon1: system-controller@6f8000 {
278 compatible = "syscon", "simple-mfd";
279 reg = <0x6f8000 0x1000>;
280 #address-cells = <1>;
283 cpu_clk: clock-cpu@278 {
284 compatible = "marvell,ap806-cpu-clock";
285 clocks = <&ap_clk 0>, <&ap_clk 1>;
290 ap_thermal: thermal-sensor@80 {
291 compatible = "marvell,armada-ap806-thermal";
293 interrupt-parent = <&sei>;
295 #thermal-sensor-cells = <1>;
302 * The thermal IP features one internal sensor plus, if applicable, one
303 * remote channel wired to one sensor per CPU.
305 * Only one thermal zone per AP/CP may trigger interrupts at a time, the
306 * first one that will have a critical trip point will be chosen.
309 ap_thermal_ic: ap-thermal-ic {
310 polling-delay-passive = <0>; /* Interrupt driven */
311 polling-delay = <0>; /* Interrupt driven */
313 thermal-sensors = <&ap_thermal 0>;
317 temperature = <100000>; /* mC degrees */
318 hysteresis = <2000>; /* mC degrees */
326 ap_thermal_cpu0: ap-thermal-cpu0 {
327 polling-delay-passive = <1000>;
328 polling-delay = <1000>;
330 thermal-sensors = <&ap_thermal 1>;
334 temperature = <85000>;
338 cpu0_emerg: cpu0-emerg {
339 temperature = <95000>;
348 cooling-device = <&cpu0 1 2>,
351 map0_emerg: map0-ermerg {
352 trip = <&cpu0_emerg>;
353 cooling-device = <&cpu0 3 3>,
359 ap_thermal_cpu1: ap-thermal-cpu1 {
360 polling-delay-passive = <1000>;
361 polling-delay = <1000>;
363 thermal-sensors = <&ap_thermal 2>;
367 temperature = <85000>;
371 cpu1_emerg: cpu1-emerg {
372 temperature = <95000>;
381 cooling-device = <&cpu0 1 2>,
384 map1_emerg: map1-emerg {
385 trip = <&cpu1_emerg>;
386 cooling-device = <&cpu0 3 3>,
392 ap_thermal_cpu2: ap-thermal-cpu2 {
393 polling-delay-passive = <1000>;
394 polling-delay = <1000>;
396 thermal-sensors = <&ap_thermal 3>;
400 temperature = <85000>;
404 cpu2_emerg: cpu2-emerg {
405 temperature = <95000>;
414 cooling-device = <&cpu2 1 2>,
417 map2_emerg: map2-emerg {
418 trip = <&cpu2_emerg>;
419 cooling-device = <&cpu2 3 3>,
425 ap_thermal_cpu3: ap-thermal-cpu3 {
426 polling-delay-passive = <1000>;
427 polling-delay = <1000>;
429 thermal-sensors = <&ap_thermal 4>;
433 temperature = <85000>;
437 cpu3_emerg: cpu3-emerg {
438 temperature = <95000>;
445 map3_hot: map3-bhot {
447 cooling-device = <&cpu2 1 2>,
450 map3_emerg: map3-emerg {
451 trip = <&cpu3_emerg>;
452 cooling-device = <&cpu2 3 3>,