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44 * Device Tree file for Marvell Armada AP806.
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
52 model = "Marvell Armada AP806";
53 compatible = "marvell,armada-ap806";
64 compatible = "arm,psci-0.2";
74 * This area matches the mapping done with a
75 * mainline U-Boot, and should be updated by the
80 reg = <0x0 0x4000000 0x0 0x200000>;
88 compatible = "simple-bus";
89 interrupt-parent = <&gic>;
92 config-space@f0000000 {
95 compatible = "simple-bus";
96 ranges = <0x0 0x0 0xf0000000 0x1000000>;
98 gic: interrupt-controller@210000 {
99 compatible = "arm,gic-400";
100 #interrupt-cells = <3>;
101 #address-cells = <1>;
104 interrupt-controller;
105 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
106 reg = <0x210000 0x10000>,
111 gic_v2m0: v2m@280000 {
112 compatible = "arm,gic-v2m-frame";
114 reg = <0x280000 0x1000>;
115 arm,msi-base-spi = <160>;
116 arm,msi-num-spis = <32>;
118 gic_v2m1: v2m@290000 {
119 compatible = "arm,gic-v2m-frame";
121 reg = <0x290000 0x1000>;
122 arm,msi-base-spi = <192>;
123 arm,msi-num-spis = <32>;
125 gic_v2m2: v2m@2a0000 {
126 compatible = "arm,gic-v2m-frame";
128 reg = <0x2a0000 0x1000>;
129 arm,msi-base-spi = <224>;
130 arm,msi-num-spis = <32>;
132 gic_v2m3: v2m@2b0000 {
133 compatible = "arm,gic-v2m-frame";
135 reg = <0x2b0000 0x1000>;
136 arm,msi-base-spi = <256>;
137 arm,msi-num-spis = <32>;
142 compatible = "arm,armv8-timer";
143 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
144 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
145 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
146 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
150 compatible = "arm,cortex-a72-pmu";
151 interrupt-parent = <&pic>;
156 compatible = "marvell,odmi-controller";
157 interrupt-controller;
159 marvell,odmi-frames = <4>;
160 reg = <0x300000 0x4000>,
164 marvell,spi-base = <128>, <136>, <144>, <152>;
168 compatible = "marvell,ap806-gicp";
169 reg = <0x3f0040 0x10>;
170 marvell,spi-ranges = <64 64>, <288 64>;
174 pic: interrupt-controller@3f0100 {
175 compatible = "marvell,armada-8k-pic";
176 reg = <0x3f0100 0x10>;
177 #interrupt-cells = <1>;
178 interrupt-controller;
179 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
183 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
184 reg = <0x400000 0x1000>,
186 msi-parent = <&gic_v2m0>;
187 clocks = <&ap_clk 3>;
192 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
193 reg = <0x420000 0x1000>,
195 msi-parent = <&gic_v2m0>;
196 clocks = <&ap_clk 3>;
201 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
202 reg = <0x440000 0x1000>,
204 msi-parent = <&gic_v2m0>;
205 clocks = <&ap_clk 3>;
210 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
211 reg = <0x460000 0x1000>,
213 msi-parent = <&gic_v2m0>;
214 clocks = <&ap_clk 3>;
219 compatible = "marvell,armada-380-spi";
220 reg = <0x510600 0x50>;
221 #address-cells = <1>;
224 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&ap_clk 3>;
230 compatible = "marvell,mv78230-i2c";
231 reg = <0x511000 0x20>;
232 #address-cells = <1>;
234 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&ap_clk 3>;
240 uart0: serial@512000 {
241 compatible = "snps,dw-apb-uart";
242 reg = <0x512000 0x100>;
244 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&ap_clk 3>;
250 uart1: serial@512100 {
251 compatible = "snps,dw-apb-uart";
252 reg = <0x512100 0x100>;
254 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&ap_clk 3>;
261 ap_sdhci0: sdhci@6e0000 {
262 compatible = "marvell,armada-ap806-sdhci";
263 reg = <0x6e0000 0x300>;
264 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
265 clock-names = "core";
266 clocks = <&ap_clk 4>;
268 marvell,xenon-phy-slow-mode;
272 ap_syscon: system-controller@6f4000 {
273 compatible = "syscon", "simple-mfd";
274 reg = <0x6f4000 0x2000>;
277 compatible = "marvell,ap806-clock";
281 ap_pinctrl: pinctrl {
282 compatible = "marvell,ap806-pinctrl";
286 compatible = "marvell,armada-8k-gpio";
291 gpio-ranges = <&ap_pinctrl 0 0 20>;