1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
5 * Device Tree file for Marvell Armada 8040 Development board platform
8 #include <dt-bindings/gpio/gpio.h>
9 #include "armada-8040.dtsi"
12 model = "Marvell Armada 8040 DB board";
13 compatible = "marvell,armada8040-db", "marvell,armada8040",
14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
17 stdout-path = "serial0:115200n8";
21 device_type = "memory";
22 reg = <0x0 0x0 0x0 0x80000000>;
26 ethernet0 = &cp0_eth0;
27 ethernet1 = &cp0_eth2;
28 ethernet2 = &cp1_eth0;
29 ethernet3 = &cp1_eth1;
34 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
35 compatible = "regulator-fixed";
36 regulator-name = "cp0-usb3h0-vbus";
37 regulator-min-microvolt = <5000000>;
38 regulator-max-microvolt = <5000000>;
40 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
43 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
44 compatible = "regulator-fixed";
45 regulator-name = "cp0-usb3h1-vbus";
46 regulator-min-microvolt = <5000000>;
47 regulator-max-microvolt = <5000000>;
49 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
52 cp0_usb3_0_phy: cp0-usb3-0-phy {
53 compatible = "usb-nop-xceiv";
54 vcc-supply = <&cp0_reg_usb3_0_vbus>;
57 cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
58 compatible = "regulator-fixed";
59 regulator-name = "cp1-usb3h0-vbus";
60 regulator-min-microvolt = <5000000>;
61 regulator-max-microvolt = <5000000>;
63 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
66 cp1_usb3_0_phy: cp1-usb3-0-phy {
67 compatible = "usb-nop-xceiv";
68 vcc-supply = <&cp1_reg_usb3_0_vbus>;
76 compatible = "jedec,spi-nor";
78 spi-max-frequency = <10000000>;
81 compatible = "fixed-partitions";
91 reg = <0x200000 0xce0000>;
97 /* Accessible over the mini-USB CON9 connector on the main board */
100 pinctrl-0 = <&uart0_pins>;
101 pinctrl-names = "default";
104 /* CON6 on CP0 expansion */
106 phys = <&cp0_comphy0 0>;
107 phy-names = "cp0-pcie0-x1-phy";
111 /* CON5 on CP0 expansion */
113 phys = <&cp0_comphy5 2>;
114 phy-names = "cp0-pcie2-x1-phy";
120 clock-frequency = <100000>;
123 expander0: pca9555@21 {
124 compatible = "nxp,pca9555";
125 pinctrl-names = "default";
132 expander1: pca9555@25 {
133 compatible = "nxp,pca9555";
134 pinctrl-names = "default";
142 /* CON4 on CP0 expansion */
147 phys = <&cp0_comphy1 0>;
148 phy-names = "cp0-sata0-0-phy";
151 phys = <&cp0_comphy3 1>;
152 phy-names = "cp0-sata0-1-phy";
156 /* CON9 on CP0 expansion */
162 usb-phy = <&cp0_usb3_0_phy>;
170 cp0_usbh1_con: connector {
171 compatible = "usb-a-connector";
172 phy-supply = <&cp0_reg_usb3_1_vbus>;
176 /* CON10 on CP0 expansion */
178 phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
179 phy-names = "usb", "utmi";
187 phy1: ethernet-phy@1 {
198 phy-mode = "10gbase-r";
209 phy-mode = "rgmii-id";
212 /* CON6 on CP1 expansion */
214 phys = <&cp1_comphy0 0>;
215 phy-names = "cp1-pcie0-x1-phy";
219 /* CON7 on CP1 expansion */
221 phys = <&cp1_comphy4 1>;
222 phy-names = "cp1-pcie1-x1-phy";
226 /* CON5 on CP1 expansion */
228 phys = <&cp1_comphy5 2>;
229 phy-names = "cp1-pcie2-x1-phy";
235 clock-frequency = <100000>;
242 compatible = "jedec,spi-nor";
244 spi-max-frequency = <20000000>;
247 compatible = "fixed-partitions";
248 #address-cells = <1>;
253 reg = <0x0 0x200000>;
256 label = "Filesystem";
257 reg = <0x200000 0xd00000>;
261 reg = <0xf00000 0x100000>;
268 * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
269 * MDIO signal of CP1.
271 &cp1_nand_controller {
272 pinctrl-0 = <&nand_pins>, <&nand_rb>;
273 pinctrl-names = "default";
279 nand-ecc-strength = <4>;
280 nand-ecc-step-size = <512>;
283 compatible = "fixed-partitions";
284 #address-cells = <1>;
293 reg = <0x200000 0xe00000>;
296 label = "Filesystem";
297 reg = <0x1000000 0x3f000000>;
303 /* CON4 on CP1 expansion */
308 phys = <&cp1_comphy1 0>;
309 phy-names = "cp1-sata0-0-phy";
312 phys = <&cp1_comphy3 1>;
313 phy-names = "cp1-sata0-1-phy";
321 /* CON9 on CP1 expansion */
323 usb-phy = <&cp1_usb3_0_phy>;
330 /* CON10 on CP1 expansion */
340 phy0: ethernet-phy@0 {
351 phy-mode = "10gbase-r";
362 phy-mode = "rgmii-id";