1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Device Tree file for Globalscale MOCHAbin
4 * Copyright (C) 2019 Globalscale technologies, Inc.
5 * Copyright (C) 2021 Sartura Ltd.
11 #include <dt-bindings/gpio/gpio.h>
12 #include "armada-7040.dtsi"
15 model = "Globalscale MOCHAbin";
16 compatible = "globalscale,mochabin", "marvell,armada7040",
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
24 ethernet0 = &cp0_eth0;
25 ethernet1 = &cp0_eth1;
26 ethernet2 = &cp0_eth2;
35 compatible = "sff,sfp";
36 i2c-bus = <&cp0_i2c1>;
37 los-gpios = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
38 mod-def0-gpios = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
39 tx-disable-gpios = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>;
40 tx-fault-gpios = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>;
45 compatible = "sff,sfp";
46 i2c-bus = <&cp0_i2c0>;
47 los-gpios = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>;
48 mod-def0-gpios = <&sfp_gpio 6 GPIO_ACTIVE_LOW>;
49 tx-disable-gpios = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>;
50 tx-fault-gpios = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>;
54 /* microUSB UART console */
58 pinctrl-0 = <&uart0_pins>;
59 pinctrl-names = "default";
68 /delete-property/ marvell,xenon-phy-slow-mode;
73 cp0_uart0_pins: cp0-uart0-pins {
74 marvell,pins = "mpp6", "mpp7";
75 marvell,function = "uart0";
78 cp0_spi0_pins: cp0-spi0-pins {
79 marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
80 marvell,function = "spi0";
83 cp0_spi1_pins: cp0-spi1-pins {
84 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
85 marvell,function = "spi1";
88 cp0_i2c0_pins: cp0-i2c0-pins {
89 marvell,pins = "mpp37", "mpp38";
90 marvell,function = "i2c0";
93 cp0_i2c1_pins: cp0-i2c1-pins {
94 marvell,pins = "mpp2", "mpp3";
95 marvell,function = "i2c1";
98 pca9554_int_pins: pca9554-int-pins {
99 marvell,pins = "mpp27";
100 marvell,function = "gpio";
103 cp0_rgmii1_pins: cp0-rgmii1-pins {
104 marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49",
105 "mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55";
106 marvell,function = "ge1";
109 is31_sdb_pins: is31-sdb-pins {
110 marvell,pins = "mpp30";
111 marvell,function = "gpio";
114 cp0_pcie_reset_pins: cp0-pcie-reset-pins {
115 marvell,pins = "mpp9";
116 marvell,function = "gpio";
119 cp0_pcie_clkreq_pins: cp0-pcie-clkreq-pins {
120 marvell,pins = "mpp5";
121 marvell,function = "pcie1";
124 cp0_switch_pins: cp0-switch-pins {
125 marvell,pins = "mpp0", "mpp1";
126 marvell,function = "gpio";
129 cp0_phy_pins: cp0-phy-pins {
130 marvell,pins = "mpp12";
131 marvell,function = "gpio";
139 pinctrl-names = "default";
140 pinctrl-0 = <&cp0_uart0_pins>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&cp0_spi0_pins>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&cp0_spi1_pins>;
159 #address-cells = <1>;
161 compatible = "jedec,spi-nor";
163 spi-max-frequency = <20000000>;
166 compatible = "fixed-partitions";
167 #address-cells = <1>;
172 reg = <0x0 0x3e0000>;
178 reg = <0x3e0000 0x10000>;
183 label = "u-boot-env";
184 reg = <0x3f0000 0x10000>;
190 /* mikroBUS, 1G SFP and GPIO expander */
194 pinctrl-names = "default";
195 pinctrl-0 = <&cp0_i2c0_pins>;
196 clock-frequency = <100000>;
198 sfp_gpio: pca9554@39 {
199 compatible = "nxp,pca9554";
200 pinctrl-names = "default";
201 pinctrl-0 = <&pca9554_int_pins>;
204 interrupt-parent = <&cp0_gpio1>;
205 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
206 interrupt-controller;
207 #interrupt-cells = <2>;
213 * IO0_0: SFP+_TX_FAULT
214 * IO0_1: SFP+_TX_DISABLE
217 * IO0_4: SFP_TX_FAULT
218 * IO0_5: SFP_TX_DISABLE
225 /* IS31FL3199, mini-PCIe and 10G SFP+ */
229 pinctrl-names = "default";
230 pinctrl-0 = <&cp0_i2c1_pins>;
231 clock-frequency = <100000>;
234 compatible = "issi,is31fl3199";
235 #address-cells = <1>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&is31_sdb_pins>;
239 shutdown-gpios = <&cp0_gpio1 30 GPIO_ACTIVE_HIGH>;
245 led-max-microamp = <20000>;
249 label = "green:led1";
264 label = "green:led2";
279 label = "green:led3";
294 eth2phy: ethernet-phy@1 {
298 pinctrl-names = "default";
299 pinctrl-0 = <&cp0_phy_pins>;
300 reset-gpios = <&cp0_gpio1 12 GPIO_ACTIVE_LOW>;
303 /* 88E6141 Topaz switch */
305 compatible = "marvell,mv88e6085";
306 #address-cells = <1>;
310 pinctrl-names = "default";
311 pinctrl-0 = <&cp0_switch_pins>;
312 reset-gpios = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
314 interrupt-parent = <&cp0_gpio1>;
315 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
318 #address-cells = <1>;
324 phy-handle = <&swphy1>;
330 phy-handle = <&swphy2>;
336 phy-handle = <&swphy3>;
342 phy-handle = <&swphy4>;
348 ethernet = <&cp0_eth1>;
349 phy-mode = "2500base-x";
350 managed = "in-band-status";
355 #address-cells = <1>;
385 phy-mode = "10gbase-r";
386 phys = <&cp0_comphy4 0>;
387 managed = "in-band-status";
391 /* Topaz switch uplink */
395 phy-mode = "2500base-x";
396 phys = <&cp0_comphy0 1>;
404 /* 1G SFP or 1G RJ45 */
408 pinctrl-names = "default";
409 pinctrl-0 = <&cp0_rgmii1_pins>;
412 phy-mode = "rgmii-id";
419 /* SMSC USB5434B hub */
423 phys = <&cp0_comphy1 0>, <&cp0_utmi0>;
424 phy-names = "cp0-usb3h0-comphy", "utmi";
435 /* 7 + 12 SATA connector (J24) */
437 phys = <&cp0_comphy2 0>;
438 phy-names = "cp0-sata0-0-phy";
441 /* M.2-2250 B-key (J39) */
443 phys = <&cp0_comphy3 1>;
444 phy-names = "cp0-sata0-1-phy";
452 pinctrl-names = "default", "clkreq";
453 pinctrl-0 = <&cp0_pcie_reset_pins>;
454 pinctrl-1 = <&cp0_pcie_clkreq_pins>;
455 phys = <&cp0_comphy5 2>;
456 phy-names = "cp0-pcie2-x1-phy";
457 reset-gpios = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
458 ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x8000000>;