1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
5 * Device Tree file for Marvell Armada 7040 Development board platform
8 #include <dt-bindings/gpio/gpio.h>
9 #include "armada-7040.dtsi"
12 model = "Marvell Armada 7040 DB board";
13 compatible = "marvell,armada7040-db", "marvell,armada7040",
14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
17 stdout-path = "serial0:115200n8";
21 device_type = "memory";
22 reg = <0x0 0x0 0x0 0x80000000>;
26 ethernet0 = &cp0_eth0;
27 ethernet1 = &cp0_eth1;
28 ethernet2 = &cp0_eth2;
31 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
32 compatible = "regulator-fixed";
33 regulator-name = "usb3h0-vbus";
34 regulator-min-microvolt = <5000000>;
35 regulator-max-microvolt = <5000000>;
37 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
40 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
41 compatible = "regulator-fixed";
42 regulator-name = "usb3h1-vbus";
43 regulator-min-microvolt = <5000000>;
44 regulator-max-microvolt = <5000000>;
46 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
49 cp0_usb3_0_phy: cp0-usb3-0-phy {
50 compatible = "usb-nop-xceiv";
51 vcc-supply = <&cp0_reg_usb3_0_vbus>;
54 cp0_usb3_1_phy: cp0-usb3-1-phy {
55 compatible = "usb-nop-xceiv";
56 vcc-supply = <&cp0_reg_usb3_1_vbus>;
62 clock-frequency = <100000>;
71 compatible = "jedec,spi-nor";
73 spi-max-frequency = <10000000>;
76 compatible = "fixed-partitions";
86 reg = <0x200000 0xce0000>;
94 pinctrl-0 = <&uart0_pins>;
95 pinctrl-names = "default";
105 clock-frequency = <100000>;
107 expander0: pca9555@21 {
108 compatible = "nxp,pca9555";
109 pinctrl-names = "default";
114 * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect
115 * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit
116 * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN
117 * IO0_3: USB2_DEVICE_DETECT
118 * IO0_4: GPIO_0 IO1_4: SD_Status
119 * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable
120 * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC
121 * IO0_7: IO1_7: SDIO_Vcntrl
126 &cp0_nand_controller {
128 * SPI on CPM and NAND have common pins on this board. We can
129 * use only one at a time. To enable the NAND (which will
130 * disable the SPI), the "status = "okay";" line have to be
133 pinctrl-0 = <&nand_pins>, <&nand_rb>;
134 pinctrl-names = "default";
138 label = "pxa3xx_nand-0";
141 nand-ecc-strength = <4>;
142 nand-ecc-step-size = <512>;
145 compatible = "fixed-partitions";
146 #address-cells = <1>;
156 reg = <0x200000 0xe00000>;
160 label = "Filesystem";
161 reg = <0x1000000 0x3f000000>;
172 #address-cells = <0x1>;
174 compatible = "jedec,spi-nor";
176 spi-max-frequency = <20000000>;
179 compatible = "fixed-partitions";
180 #address-cells = <1>;
185 reg = <0x0 0x200000>;
189 label = "Filesystem";
190 reg = <0x200000 0xe00000>;
201 usb-phy = <&cp0_usb3_0_phy>;
206 usb-phy = <&cp0_usb3_1_phy>;
221 cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
227 phy0: ethernet-phy@0 {
230 phy1: ethernet-phy@1 {
242 phy-mode = "10gbase-kr";
243 /* Generic PHY, providing serdes lanes */
244 phys = <&cp0_comphy2 0>;
257 /* Generic PHY, providing serdes lanes */
258 phys = <&cp0_comphy0 1>;
264 phy-mode = "rgmii-id";