1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
5 * Copyright (C) 2016 Marvell
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 model = "Marvell Armada 37xx SoC";
15 compatible = "marvell,armada3700";
16 interrupt-parent = <&gic>;
31 * The PSCI firmware region depicted below is the default one
32 * and should be updated by the bootloader.
35 reg = <0 0x4000000 0 0x200000>;
40 reg = <0 0x4400000 0 0x1000000>;
50 compatible = "arm,cortex-a53";
52 clocks = <&nb_periph_clk 16>;
53 enable-method = "psci";
58 compatible = "arm,psci-0.2";
63 compatible = "arm,armv8-timer";
64 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
71 compatible = "arm,armv8-pmuv3";
72 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
76 compatible = "simple-bus";
81 internal-regs@d0000000 {
84 compatible = "simple-bus";
85 /* 32M internal register @ 0xd000_0000 */
86 ranges = <0x0 0x0 0xd0000000 0x2000000>;
89 compatible = "marvell,armada-3700-wdt";
91 marvell,system-controller = <&cpu_misc>;
95 cpu_misc: system-controller@d000 {
96 compatible = "marvell,armada-3700-cpu-misc",
98 reg = <0xd000 0x1000>;
102 compatible = "marvell,armada-3700-spi";
103 #address-cells = <1>;
105 reg = <0x10600 0xA00>;
106 clocks = <&nb_periph_clk 7>;
107 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
113 compatible = "marvell,armada-3700-i2c";
114 reg = <0x11000 0x24>;
115 #address-cells = <1>;
117 clocks = <&nb_periph_clk 10>;
118 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
124 compatible = "marvell,armada-3700-i2c";
125 reg = <0x11080 0x24>;
126 #address-cells = <1>;
128 clocks = <&nb_periph_clk 9>;
129 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
135 compatible = "marvell,armada-3700-avs",
137 reg = <0x11500 0x40>;
140 uartclk: clock-controller@12010 {
141 compatible = "marvell,armada-3700-uart-clock";
142 reg = <0x12010 0x4>, <0x12210 0x4>;
143 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
144 <&tbg 3>, <&xtalclk>;
145 clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S",
150 uart0: serial@12000 {
151 compatible = "marvell,armada-3700-uart";
152 reg = <0x12000 0x18>;
153 clocks = <&uartclk 0>;
155 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
158 interrupt-names = "uart-sum", "uart-tx", "uart-rx";
162 uart1: serial@12200 {
163 compatible = "marvell,armada-3700-uart-ext";
164 reg = <0x12200 0x30>;
165 clocks = <&uartclk 1>;
167 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
168 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
169 interrupt-names = "uart-tx", "uart-rx";
173 nb_periph_clk: nb-periph-clk@13000 {
174 compatible = "marvell,armada-3700-periph-clock-nb",
176 reg = <0x13000 0x100>;
177 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
178 <&tbg 3>, <&xtalclk>;
182 sb_periph_clk: sb-periph-clk@18000 {
183 compatible = "marvell,armada-3700-periph-clock-sb";
184 reg = <0x18000 0x100>;
185 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
186 <&tbg 3>, <&xtalclk>;
191 compatible = "marvell,armada-3700-tbg-clock";
192 reg = <0x13200 0x100>;
197 pinctrl_nb: pinctrl@13800 {
198 compatible = "marvell,armada3710-nb-pinctrl",
199 "syscon", "simple-mfd";
200 reg = <0x13800 0x100>, <0x13C00 0x20>;
204 gpio-ranges = <&pinctrl_nb 0 0 36>;
206 interrupt-controller;
207 #interrupt-cells = <2>;
209 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
224 compatible = "marvell,armada-3700-xtal-clock";
225 clock-output-names = "xtal";
229 spi_quad_pins: spi-quad-pins {
234 spi_cs1_pins: spi-cs1-pins {
239 i2c1_pins: i2c1-pins {
244 i2c2_pins: i2c2-pins {
249 uart1_pins: uart1-pins {
254 uart2_pins: uart2-pins {
265 nb_pm: syscon@14000 {
266 compatible = "marvell,armada-3700-nb-pm",
268 reg = <0x14000 0x60>;
272 compatible = "marvell,comphy-a3700";
273 reg = <0x18300 0x300>,
277 reg-names = "comphy",
281 #address-cells = <1>;
284 clock-names = "xtal";
302 pinctrl_sb: pinctrl@18800 {
303 compatible = "marvell,armada3710-sb-pinctrl",
304 "syscon", "simple-mfd";
305 reg = <0x18800 0x100>, <0x18C00 0x20>;
309 gpio-ranges = <&pinctrl_sb 0 0 30>;
311 interrupt-controller;
312 #interrupt-cells = <2>;
314 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
321 rgmii_pins: mii-pins {
331 sdio_pins: sdio-pins {
336 pcie_reset_pins: pcie-reset-pins {
337 groups = "pcie1"; /* this actually controls "pcie1_reset" */
341 pcie_clkreq_pins: pcie-clkreq-pins {
342 groups = "pcie1_clkreq";
347 eth0: ethernet@30000 {
348 compatible = "marvell,armada-3700-neta";
349 reg = <0x30000 0x4000>;
350 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&sb_periph_clk 8>;
356 #address-cells = <1>;
358 compatible = "marvell,orion-mdio";
362 eth1: ethernet@40000 {
363 compatible = "marvell,armada-3700-neta";
364 reg = <0x40000 0x4000>;
365 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&sb_periph_clk 7>;
371 compatible = "marvell,armada3700-xhci",
373 reg = <0x58000 0x4000>;
374 marvell,usb-misc-reg = <&usb32_syscon>;
375 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&sb_periph_clk 12>;
377 phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
378 phy-names = "usb3-phy", "usb2-utmi-otg-phy";
382 usb2_utmi_otg_phy: phy@5d000 {
383 compatible = "marvell,a3700-utmi-otg-phy";
384 reg = <0x5d000 0x800>;
385 marvell,usb-misc-reg = <&usb32_syscon>;
389 usb32_syscon: system-controller@5d800 {
390 compatible = "marvell,armada-3700-usb2-host-device-misc",
392 reg = <0x5d800 0x800>;
396 compatible = "marvell,armada-3700-ehci";
397 reg = <0x5e000 0x1000>;
398 marvell,usb-misc-reg = <&usb2_syscon>;
399 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
400 phys = <&usb2_utmi_host_phy>;
401 phy-names = "usb2-utmi-host-phy";
405 usb2_utmi_host_phy: phy@5f000 {
406 compatible = "marvell,a3700-utmi-host-phy";
407 reg = <0x5f000 0x800>;
408 marvell,usb-misc-reg = <&usb2_syscon>;
412 usb2_syscon: system-controller@5f800 {
413 compatible = "marvell,armada-3700-usb2-host-misc",
415 reg = <0x5f800 0x800>;
419 compatible = "marvell,armada-3700-xor";
420 reg = <0x60900 0x100>,
424 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
427 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
431 crypto: crypto@90000 {
432 compatible = "inside-secure,safexcel-eip97ies";
433 reg = <0x90000 0x20000>;
434 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
440 interrupt-names = "mem", "ring0", "ring1",
441 "ring2", "ring3", "eip";
442 clocks = <&nb_periph_clk 15>;
445 rwtm: mailbox@b0000 {
446 compatible = "marvell,armada-3700-rwtm-mailbox";
447 reg = <0xb0000 0x100>;
448 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
453 compatible = "marvell,armada-3700-sdhci",
454 "marvell,sdhci-xenon";
455 reg = <0xd0000 0x300>,
457 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&nb_periph_clk 0>;
459 clock-names = "core";
464 compatible = "marvell,armada-3700-sdhci",
465 "marvell,sdhci-xenon";
466 reg = <0xd8000 0x300>,
468 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&nb_periph_clk 0>;
470 clock-names = "core";
475 compatible = "marvell,armada-3700-ahci";
476 reg = <0xe0000 0x178>;
477 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&nb_periph_clk 1>;
480 phy-names = "sata-phy";
484 gic: interrupt-controller@1d00000 {
485 compatible = "arm,gic-v3";
486 #interrupt-cells = <3>;
487 interrupt-controller;
488 reg = <0x1d00000 0x10000>, /* GICD */
489 <0x1d40000 0x40000>, /* GICR */
490 <0x1d80000 0x2000>, /* GICC */
491 <0x1d90000 0x2000>, /* GICH */
492 <0x1da0000 0x20000>; /* GICV */
493 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
497 pcie0: pcie@d0070000 {
498 compatible = "marvell,armada-3700-pcie";
501 reg = <0 0xd0070000 0 0x20000>;
502 #address-cells = <3>;
504 bus-range = <0x00 0xff>;
505 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
506 #interrupt-cells = <1>;
507 clocks = <&sb_periph_clk 13>;
508 msi-parent = <&pcie0>;
511 * The 128 MiB address range [0xe8000000-0xf0000000] is
512 * dedicated for PCIe and can be assigned to 8 windows
513 * with size a power of two. Use one 64 KiB window for
514 * IO at the end and the remaining seven windows
515 * (totaling 127 MiB) for MEM.
517 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */
518 0x81000000 0 0x00000000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */
519 interrupt-map-mask = <0 0 0 7>;
520 interrupt-map = <0 0 0 1 &pcie_intc 0>,
521 <0 0 0 2 &pcie_intc 1>,
522 <0 0 0 3 &pcie_intc 2>,
523 <0 0 0 4 &pcie_intc 3>;
524 max-link-speed = <2>;
526 pcie_intc: interrupt-controller {
527 interrupt-controller;
528 #interrupt-cells = <1>;
535 compatible = "marvell,armada-3700-rwtm-firmware";