1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
5 * Copyright (C) 2016 Marvell
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 model = "Marvell Armada 37xx SoC";
15 compatible = "marvell,armada3700";
16 interrupt-parent = <&gic>;
31 * The PSCI firmware region depicted below is the default one
32 * and should be updated by the bootloader.
35 reg = <0 0x4000000 0 0x200000>;
45 compatible = "arm,cortex-a53";
47 clocks = <&nb_periph_clk 16>;
48 enable-method = "psci";
53 compatible = "arm,psci-0.2";
58 compatible = "arm,armv8-timer";
59 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
66 compatible = "arm,armv8-pmuv3";
67 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
71 compatible = "simple-bus";
76 internal-regs@d0000000 {
79 compatible = "simple-bus";
80 /* 32M internal register @ 0xd000_0000 */
81 ranges = <0x0 0x0 0xd0000000 0x2000000>;
84 compatible = "marvell,armada-3700-wdt";
86 marvell,system-controller = <&cpu_misc>;
90 cpu_misc: system-controller@d000 {
91 compatible = "marvell,armada-3700-cpu-misc",
93 reg = <0xd000 0x1000>;
97 compatible = "marvell,armada-3700-spi";
100 reg = <0x10600 0xA00>;
101 clocks = <&nb_periph_clk 7>;
102 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
108 compatible = "marvell,armada-3700-i2c";
109 reg = <0x11000 0x24>;
110 #address-cells = <1>;
112 clocks = <&nb_periph_clk 10>;
113 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
119 compatible = "marvell,armada-3700-i2c";
120 reg = <0x11080 0x24>;
121 #address-cells = <1>;
123 clocks = <&nb_periph_clk 9>;
124 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
130 compatible = "marvell,armada-3700-avs",
132 reg = <0x11500 0x40>;
135 uartclk: clock-controller@12010 {
136 compatible = "marvell,armada-3700-uart-clock";
137 reg = <0x12010 0x4>, <0x12210 0x4>;
138 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
139 <&tbg 3>, <&xtalclk>;
140 clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S",
145 uart0: serial@12000 {
146 compatible = "marvell,armada-3700-uart";
147 reg = <0x12000 0x18>;
148 clocks = <&uartclk 0>;
150 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
153 interrupt-names = "uart-sum", "uart-tx", "uart-rx";
157 uart1: serial@12200 {
158 compatible = "marvell,armada-3700-uart-ext";
159 reg = <0x12200 0x30>;
160 clocks = <&uartclk 1>;
162 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
163 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
164 interrupt-names = "uart-tx", "uart-rx";
168 nb_periph_clk: nb-periph-clk@13000 {
169 compatible = "marvell,armada-3700-periph-clock-nb",
171 reg = <0x13000 0x100>;
172 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
173 <&tbg 3>, <&xtalclk>;
177 sb_periph_clk: sb-periph-clk@18000 {
178 compatible = "marvell,armada-3700-periph-clock-sb";
179 reg = <0x18000 0x100>;
180 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
181 <&tbg 3>, <&xtalclk>;
186 compatible = "marvell,armada-3700-tbg-clock";
187 reg = <0x13200 0x100>;
192 pinctrl_nb: pinctrl@13800 {
193 compatible = "marvell,armada3710-nb-pinctrl",
194 "syscon", "simple-mfd";
195 reg = <0x13800 0x100>, <0x13C00 0x20>;
199 gpio-ranges = <&pinctrl_nb 0 0 36>;
201 interrupt-controller;
202 #interrupt-cells = <2>;
204 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
219 compatible = "marvell,armada-3700-xtal-clock";
220 clock-output-names = "xtal";
224 spi_quad_pins: spi-quad-pins {
229 spi_cs1_pins: spi-cs1-pins {
234 i2c1_pins: i2c1-pins {
239 i2c2_pins: i2c2-pins {
244 uart1_pins: uart1-pins {
249 uart2_pins: uart2-pins {
260 nb_pm: syscon@14000 {
261 compatible = "marvell,armada-3700-nb-pm",
263 reg = <0x14000 0x60>;
267 compatible = "marvell,comphy-a3700";
268 reg = <0x18300 0x300>,
272 reg-names = "comphy",
276 #address-cells = <1>;
279 clock-names = "xtal";
297 pinctrl_sb: pinctrl@18800 {
298 compatible = "marvell,armada3710-sb-pinctrl",
299 "syscon", "simple-mfd";
300 reg = <0x18800 0x100>, <0x18C00 0x20>;
304 gpio-ranges = <&pinctrl_sb 0 0 30>;
306 interrupt-controller;
307 #interrupt-cells = <2>;
309 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
316 rgmii_pins: mii-pins {
326 sdio_pins: sdio-pins {
331 pcie_reset_pins: pcie-reset-pins {
332 groups = "pcie1"; /* this actually controls "pcie1_reset" */
336 pcie_clkreq_pins: pcie-clkreq-pins {
337 groups = "pcie1_clkreq";
342 eth0: ethernet@30000 {
343 compatible = "marvell,armada-3700-neta";
344 reg = <0x30000 0x4000>;
345 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&sb_periph_clk 8>;
351 #address-cells = <1>;
353 compatible = "marvell,orion-mdio";
357 eth1: ethernet@40000 {
358 compatible = "marvell,armada-3700-neta";
359 reg = <0x40000 0x4000>;
360 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&sb_periph_clk 7>;
366 compatible = "marvell,armada3700-xhci",
368 reg = <0x58000 0x4000>;
369 marvell,usb-misc-reg = <&usb32_syscon>;
370 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&sb_periph_clk 12>;
372 phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
373 phy-names = "usb3-phy", "usb2-utmi-otg-phy";
377 usb2_utmi_otg_phy: phy@5d000 {
378 compatible = "marvell,a3700-utmi-otg-phy";
379 reg = <0x5d000 0x800>;
380 marvell,usb-misc-reg = <&usb32_syscon>;
384 usb32_syscon: system-controller@5d800 {
385 compatible = "marvell,armada-3700-usb2-host-device-misc",
387 reg = <0x5d800 0x800>;
391 compatible = "marvell,armada-3700-ehci";
392 reg = <0x5e000 0x1000>;
393 marvell,usb-misc-reg = <&usb2_syscon>;
394 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
395 phys = <&usb2_utmi_host_phy>;
396 phy-names = "usb2-utmi-host-phy";
400 usb2_utmi_host_phy: phy@5f000 {
401 compatible = "marvell,a3700-utmi-host-phy";
402 reg = <0x5f000 0x800>;
403 marvell,usb-misc-reg = <&usb2_syscon>;
407 usb2_syscon: system-controller@5f800 {
408 compatible = "marvell,armada-3700-usb2-host-misc",
410 reg = <0x5f800 0x800>;
414 compatible = "marvell,armada-3700-xor";
415 reg = <0x60900 0x100>,
419 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
422 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
426 crypto: crypto@90000 {
427 compatible = "inside-secure,safexcel-eip97ies";
428 reg = <0x90000 0x20000>;
429 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
435 interrupt-names = "ring0", "ring1", "ring2",
436 "ring3", "eip", "mem";
437 clocks = <&nb_periph_clk 15>;
440 rwtm: mailbox@b0000 {
441 compatible = "marvell,armada-3700-rwtm-mailbox";
442 reg = <0xb0000 0x100>;
443 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
448 compatible = "marvell,armada-3700-sdhci",
449 "marvell,sdhci-xenon";
450 reg = <0xd0000 0x300>,
452 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&nb_periph_clk 0>;
454 clock-names = "core";
459 compatible = "marvell,armada-3700-sdhci",
460 "marvell,sdhci-xenon";
461 reg = <0xd8000 0x300>,
463 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&nb_periph_clk 0>;
465 clock-names = "core";
470 compatible = "marvell,armada-3700-ahci";
471 reg = <0xe0000 0x178>;
472 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&nb_periph_clk 1>;
475 phy-names = "sata-phy";
479 gic: interrupt-controller@1d00000 {
480 compatible = "arm,gic-v3";
481 #interrupt-cells = <3>;
482 interrupt-controller;
483 reg = <0x1d00000 0x10000>, /* GICD */
484 <0x1d40000 0x40000>, /* GICR */
485 <0x1d80000 0x2000>, /* GICC */
486 <0x1d90000 0x2000>, /* GICH */
487 <0x1da0000 0x20000>; /* GICV */
488 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
492 pcie0: pcie@d0070000 {
493 compatible = "marvell,armada-3700-pcie";
496 reg = <0 0xd0070000 0 0x20000>;
497 #address-cells = <3>;
499 bus-range = <0x00 0xff>;
500 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
501 #interrupt-cells = <1>;
502 clocks = <&sb_periph_clk 13>;
503 msi-parent = <&pcie0>;
506 * The 128 MiB address range [0xe8000000-0xf0000000] is
507 * dedicated for PCIe and can be assigned to 8 windows
508 * with size a power of two. Use one 64 KiB window for
509 * IO at the end and the remaining seven windows
510 * (totaling 127 MiB) for MEM.
512 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */
513 0x81000000 0 0x00000000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */
514 interrupt-map-mask = <0 0 0 7>;
515 interrupt-map = <0 0 0 1 &pcie_intc 0>,
516 <0 0 0 2 &pcie_intc 1>,
517 <0 0 0 3 &pcie_intc 2>,
518 <0 0 0 4 &pcie_intc 3>;
519 max-link-speed = <2>;
521 pcie_intc: interrupt-controller {
522 interrupt-controller;
523 #interrupt-cells = <1>;
530 compatible = "marvell,armada-3700-rwtm-firmware";