2 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
4 * Copyright (C) 2016 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This file is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 model = "Marvell Armada 37xx SoC";
51 compatible = "marvell,armada3700";
52 interrupt-parent = <&gic>;
65 compatible = "arm,cortex-a53", "arm,armv8";
67 enable-method = "psci";
72 compatible = "arm,psci-0.2";
77 compatible = "arm,armv8-timer";
78 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
85 compatible = "arm,armv8-pmuv3";
86 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
90 compatible = "simple-bus";
95 internal-regs@d0000000 {
98 compatible = "simple-bus";
99 /* 32M internal register @ 0xd000_0000 */
100 ranges = <0x0 0x0 0xd0000000 0x2000000>;
103 compatible = "marvell,armada-3700-spi";
104 #address-cells = <1>;
106 reg = <0x10600 0xA00>;
107 clocks = <&nb_periph_clk 7>;
108 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
114 compatible = "marvell,armada-3700-i2c";
115 reg = <0x11000 0x24>;
116 #address-cells = <1>;
118 clocks = <&nb_periph_clk 10>;
119 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
125 compatible = "marvell,armada-3700-i2c";
126 reg = <0x11080 0x24>;
127 #address-cells = <1>;
129 clocks = <&nb_periph_clk 9>;
130 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
135 uart0: serial@12000 {
136 compatible = "marvell,armada-3700-uart";
137 reg = <0x12000 0x200>;
138 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
142 nb_periph_clk: nb-periph-clk@13000 {
143 compatible = "marvell,armada-3700-periph-clock-nb";
144 reg = <0x13000 0x100>;
145 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
146 <&tbg 3>, <&xtalclk>;
150 sb_periph_clk: sb-periph-clk@18000 {
151 compatible = "marvell,armada-3700-periph-clock-sb";
152 reg = <0x18000 0x100>;
153 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
154 <&tbg 3>, <&xtalclk>;
159 compatible = "marvell,armada-3700-tbg-clock";
160 reg = <0x13200 0x100>;
165 pinctrl_nb: pinctrl@13800 {
166 compatible = "marvell,armada3710-nb-pinctrl",
167 "syscon", "simple-mfd";
168 reg = <0x13800 0x100>, <0x13C00 0x20>;
171 gpio-ranges = <&pinctrl_nb 0 0 36>;
174 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
190 compatible = "marvell,armada-3700-xtal-clock";
191 clock-output-names = "xtal";
195 spi_quad_pins: spi-quad-pins {
200 i2c1_pins: i2c1-pins {
205 i2c2_pins: i2c2-pins {
210 uart1_pins: uart1-pins {
215 uart2_pins: uart2-pins {
221 pinctrl_sb: pinctrl@18800 {
222 compatible = "marvell,armada3710-sb-pinctrl",
223 "syscon", "simple-mfd";
224 reg = <0x18800 0x100>, <0x18C00 0x20>;
227 gpio-ranges = <&pinctrl_sb 0 0 30>;
230 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
237 rgmii_pins: mii-pins {
242 pcie_reset_pins: pcie-reset-pins {
247 pcie_clkreq_pins: pcie-clkreq-pins {
248 groups = "pcie1_clkreq";
253 eth0: ethernet@30000 {
254 compatible = "marvell,armada-3700-neta";
255 reg = <0x30000 0x4000>;
256 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&sb_periph_clk 8>;
262 #address-cells = <1>;
264 compatible = "marvell,orion-mdio";
268 eth1: ethernet@40000 {
269 compatible = "marvell,armada-3700-neta";
270 reg = <0x40000 0x4000>;
271 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
272 clocks = <&sb_periph_clk 7>;
277 compatible = "marvell,armada3700-xhci",
279 reg = <0x58000 0x4000>;
280 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&sb_periph_clk 12>;
286 compatible = "marvell,armada-3700-ehci";
287 reg = <0x5e000 0x2000>;
288 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
293 compatible = "marvell,armada-3700-xor";
294 reg = <0x60900 0x100>,
298 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
301 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
305 sdhci1: sdhci@d0000 {
306 compatible = "marvell,armada-3700-sdhci",
307 "marvell,sdhci-xenon";
308 reg = <0xd0000 0x300>,
310 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&nb_periph_clk 0>;
312 clock-names = "core";
316 sdhci0: sdhci@d8000 {
317 compatible = "marvell,armada-3700-sdhci",
318 "marvell,sdhci-xenon";
319 reg = <0xd8000 0x300>,
321 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&nb_periph_clk 0>;
323 clock-names = "core";
328 compatible = "marvell,armada-3700-ahci";
329 reg = <0xe0000 0x2000>;
330 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
334 gic: interrupt-controller@1d00000 {
335 compatible = "arm,gic-v3";
336 #interrupt-cells = <3>;
337 interrupt-controller;
338 reg = <0x1d00000 0x10000>, /* GICD */
339 <0x1d40000 0x40000>, /* GICR */
340 <0x1d80000 0x2000>, /* GICC */
341 <0x1d90000 0x2000>, /* GICH */
342 <0x1da0000 0x20000>; /* GICV */
343 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
347 pcie0: pcie@d0070000 {
348 compatible = "marvell,armada-3700-pcie";
351 reg = <0 0xd0070000 0 0x20000>;
352 #address-cells = <3>;
354 bus-range = <0x00 0xff>;
355 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
356 #interrupt-cells = <1>;
357 msi-parent = <&pcie0>;
360 * The 128 MiB address range [0xe8000000-0xf0000000] is
361 * dedicated for PCIe and can be assigned to 8 windows
362 * with size a power of two. Use one 64 KiB window for
363 * IO at the end and the remaining seven windows
364 * (totaling 127 MiB) for MEM.
366 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */
367 0x81000000 0 0xefff0000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */
368 interrupt-map-mask = <0 0 0 7>;
369 interrupt-map = <0 0 0 1 &pcie_intc 0>,
370 <0 0 0 2 &pcie_intc 1>,
371 <0 0 0 3 &pcie_intc 2>,
372 <0 0 0 4 &pcie_intc 3>;
373 pcie_intc: interrupt-controller {
374 interrupt-controller;
375 #interrupt-cells = <1>;