1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
5 * Copyright (C) 2016 Marvell
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 model = "Marvell Armada 37xx SoC";
15 compatible = "marvell,armada3700";
16 interrupt-parent = <&gic>;
31 * The PSCI firmware region depicted below is the default one
32 * and should be updated by the bootloader.
35 reg = <0 0x4000000 0 0x200000>;
45 compatible = "arm,cortex-a53", "arm,armv8";
47 clocks = <&nb_periph_clk 16>;
48 enable-method = "psci";
53 compatible = "arm,psci-0.2";
58 compatible = "arm,armv8-timer";
59 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
66 compatible = "arm,armv8-pmuv3";
67 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
71 compatible = "simple-bus";
76 internal-regs@d0000000 {
79 compatible = "simple-bus";
80 /* 32M internal register @ 0xd000_0000 */
81 ranges = <0x0 0x0 0xd0000000 0x2000000>;
84 compatible = "marvell,armada-3700-spi";
87 reg = <0x10600 0xA00>;
88 clocks = <&nb_periph_clk 7>;
89 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
95 compatible = "marvell,armada-3700-i2c";
99 clocks = <&nb_periph_clk 10>;
100 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
106 compatible = "marvell,armada-3700-i2c";
107 reg = <0x11080 0x24>;
108 #address-cells = <1>;
110 clocks = <&nb_periph_clk 9>;
111 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
117 compatible = "marvell,armada-3700-avs",
119 reg = <0x11500 0x40>;
122 uart0: serial@12000 {
123 compatible = "marvell,armada-3700-uart";
124 reg = <0x12000 0x18>;
127 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
130 interrupt-names = "uart-sum", "uart-tx", "uart-rx";
134 uart1: serial@12200 {
135 compatible = "marvell,armada-3700-uart-ext";
136 reg = <0x12200 0x30>;
139 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
140 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
141 interrupt-names = "uart-tx", "uart-rx";
145 nb_periph_clk: nb-periph-clk@13000 {
146 compatible = "marvell,armada-3700-periph-clock-nb",
148 reg = <0x13000 0x100>;
149 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
150 <&tbg 3>, <&xtalclk>;
154 sb_periph_clk: sb-periph-clk@18000 {
155 compatible = "marvell,armada-3700-periph-clock-sb";
156 reg = <0x18000 0x100>;
157 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
158 <&tbg 3>, <&xtalclk>;
163 compatible = "marvell,armada-3700-tbg-clock";
164 reg = <0x13200 0x100>;
169 pinctrl_nb: pinctrl@13800 {
170 compatible = "marvell,armada3710-nb-pinctrl",
171 "syscon", "simple-mfd";
172 reg = <0x13800 0x100>, <0x13C00 0x20>;
176 gpio-ranges = <&pinctrl_nb 0 0 36>;
178 interrupt-controller;
179 #interrupt-cells = <2>;
181 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
196 compatible = "marvell,armada-3700-xtal-clock";
197 clock-output-names = "xtal";
201 spi_quad_pins: spi-quad-pins {
206 i2c1_pins: i2c1-pins {
211 i2c2_pins: i2c2-pins {
216 uart1_pins: uart1-pins {
221 uart2_pins: uart2-pins {
227 nb_pm: syscon@14000 {
228 compatible = "marvell,armada-3700-nb-pm",
230 reg = <0x14000 0x60>;
233 pinctrl_sb: pinctrl@18800 {
234 compatible = "marvell,armada3710-sb-pinctrl",
235 "syscon", "simple-mfd";
236 reg = <0x18800 0x100>, <0x18C00 0x20>;
240 gpio-ranges = <&pinctrl_sb 0 0 30>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
245 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
252 rgmii_pins: mii-pins {
257 pcie_reset_pins: pcie-reset-pins {
262 pcie_clkreq_pins: pcie-clkreq-pins {
263 groups = "pcie1_clkreq";
268 eth0: ethernet@30000 {
269 compatible = "marvell,armada-3700-neta";
270 reg = <0x30000 0x4000>;
271 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
272 clocks = <&sb_periph_clk 8>;
277 #address-cells = <1>;
279 compatible = "marvell,orion-mdio";
283 eth1: ethernet@40000 {
284 compatible = "marvell,armada-3700-neta";
285 reg = <0x40000 0x4000>;
286 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&sb_periph_clk 7>;
292 compatible = "marvell,armada3700-xhci",
294 reg = <0x58000 0x4000>;
295 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&sb_periph_clk 12>;
301 compatible = "marvell,armada-3700-ehci";
302 reg = <0x5e000 0x2000>;
303 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
308 compatible = "marvell,armada-3700-xor";
309 reg = <0x60900 0x100>,
313 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
316 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
320 crypto: crypto@90000 {
321 compatible = "inside-secure,safexcel-eip97ies";
322 reg = <0x90000 0x20000>;
323 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
329 interrupt-names = "mem", "ring0", "ring1",
330 "ring2", "ring3", "eip";
331 clocks = <&nb_periph_clk 15>;
334 sdhci1: sdhci@d0000 {
335 compatible = "marvell,armada-3700-sdhci",
336 "marvell,sdhci-xenon";
337 reg = <0xd0000 0x300>,
339 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&nb_periph_clk 0>;
341 clock-names = "core";
345 sdhci0: sdhci@d8000 {
346 compatible = "marvell,armada-3700-sdhci",
347 "marvell,sdhci-xenon";
348 reg = <0xd8000 0x300>,
350 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&nb_periph_clk 0>;
352 clock-names = "core";
357 compatible = "marvell,armada-3700-ahci";
358 reg = <0xe0000 0x2000>;
359 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
363 gic: interrupt-controller@1d00000 {
364 compatible = "arm,gic-v3";
365 #interrupt-cells = <3>;
366 interrupt-controller;
367 reg = <0x1d00000 0x10000>, /* GICD */
368 <0x1d40000 0x40000>, /* GICR */
369 <0x1d80000 0x2000>, /* GICC */
370 <0x1d90000 0x2000>, /* GICH */
371 <0x1da0000 0x20000>; /* GICV */
372 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
376 pcie0: pcie@d0070000 {
377 compatible = "marvell,armada-3700-pcie";
380 reg = <0 0xd0070000 0 0x20000>;
381 #address-cells = <3>;
383 bus-range = <0x00 0xff>;
384 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
385 #interrupt-cells = <1>;
386 msi-parent = <&pcie0>;
389 * The 128 MiB address range [0xe8000000-0xf0000000] is
390 * dedicated for PCIe and can be assigned to 8 windows
391 * with size a power of two. Use one 64 KiB window for
392 * IO at the end and the remaining seven windows
393 * (totaling 127 MiB) for MEM.
395 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */
396 0x81000000 0 0xefff0000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */
397 interrupt-map-mask = <0 0 0 7>;
398 interrupt-map = <0 0 0 1 &pcie_intc 0>,
399 <0 0 0 2 &pcie_intc 1>,
400 <0 0 0 3 &pcie_intc 2>,
401 <0 0 0 4 &pcie_intc 3>;
402 pcie_intc: interrupt-controller {
403 interrupt-controller;
404 #interrupt-cells = <1>;