arch/arm64/boot/dts/marvell/armada-37xx.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 37xx family of SoCs.
   3  *
   4  * Copyright (C) 2016 Marvell
   5  *
   6  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   7  *
   8  * This file is dual-licensed: you can use it either under the terms
   9  * of the GPL or the X11 license, at your option. Note that this dual
  10  * licensing only applies to this file, and not this project as a
  11  * whole.
  12  *
  13  *  a) This file is free software; you can redistribute it and/or
  14  *     modify it under the terms of the GNU General Public License as
  15  *     published by the Free Software Foundation; either version 2 of the
  16  *     License, or (at your option) any later version.
  17  *
  18  *     This file is distributed in the hope that it will be useful
  19  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *     GNU General Public License for more details.
  22  *
  23  * Or, alternatively
  24  *
  25  *  b) Permission is hereby granted, free of charge, to any person
  26  *     obtaining a copy of this software and associated documentation
  27  *     files (the "Software"), to deal in the Software without
  28  *     restriction, including without limitation the rights to use
  29  *     copy, modify, merge, publish, distribute, sublicense, and/or
  30  *     sell copies of the Software, and to permit persons to whom the
  31  *     Software is furnished to do so, subject to the following
  32  *     conditions:
  33  *
  34  *     The above copyright notice and this permission notice shall be
  35  *     included in all copies or substantial portions of the Software.
  36  *
  37  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44  *     OTHER DEALINGS IN THE SOFTWARE.
  45  */
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48
  49 / {
  50         model = "Marvell Armada 37xx SoC";
  51         compatible = "marvell,armada3700";
  52         interrupt-parent = <&gic>;
  53         #address-cells = <2>;
  54         #size-cells = <2>;
  55
  56         aliases {
  57                 serial0 = &uart0;
  58         };
  59
  60         cpus {
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63                 cpu@0 {
  64                         device_type = "cpu";
  65                         compatible = "arm,cortex-a53", "arm,armv8";
  66                         reg = <0>;
  67                         enable-method = "psci";
  68                 };
  69         };
  70
  71         psci {
  72                 compatible = "arm,psci-0.2";
  73                 method = "smc";
  74         };
  75
  76         timer {
  77                 compatible = "arm,armv8-timer";
  78                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
  79                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
  82         };
  83
  84         soc {
  85                 compatible = "simple-bus";
  86                 #address-cells = <2>;
  87                 #size-cells = <2>;
  88                 ranges;
  89
  90                 internal-regs {
  91                         #address-cells = <1>;
  92                         #size-cells = <1>;
  93                         compatible = "simple-bus";
  94                         /* 32M internal register @ 0xd000_0000 */
  95                         ranges = <0x0 0x0 0xd0000000 0x2000000>;
  96
  97                         uart0: serial@12000 {
  98                                 compatible = "marvell,armada-3700-uart";
  99                                 reg = <0x12000 0x200>;
 100                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 101                                 status = "disabled";
 102                         };
 103
 104                         nb_periph_clk: nb-periph-clk@13000 {
 105                                 compatible = "marvell,armada-3700-periph-clock-nb";
 106                                 reg = <0x13000 0x100>;
 107                                 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
 108                                 <&tbg 3>, <&xtalclk>;
 109                                 #clock-cells = <1>;
 110                         };
 111
 112                         sb_periph_clk: sb-periph-clk@18000 {
 113                                 compatible = "marvell,armada-3700-periph-clock-sb";
 114                                 reg = <0x18000 0x100>;
 115                                 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
 116                                 <&tbg 3>, <&xtalclk>;
 117                                 #clock-cells = <1>;
 118                         };
 119
 120                         tbg: tbg@13200 {
 121                                 compatible = "marvell,armada-3700-tbg-clock";
 122                                 reg = <0x13200 0x100>;
 123                                 clocks = <&xtalclk>;
 124                                 #clock-cells = <1>;
 125                         };
 126
 127                         gpio1: gpio@13800 {
 128                                 compatible = "marvell,mvebu-gpio-3700",
 129                                 "syscon", "simple-mfd";
 130                                 reg = <0x13800 0x500>;
 131
 132                                 xtalclk: xtal-clk {
 133                                         compatible = "marvell,armada-3700-xtal-clock";
 134                                         clock-output-names = "xtal";
 135                                         #clock-cells = <0>;
 136                                 };
 137                         };
 138
 139                         usb3: usb@58000 {
 140                                 compatible = "marvell,armada3700-xhci",
 141                                 "generic-xhci";
 142                                 reg = <0x58000 0x4000>;
 143                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 144                                 status = "disabled";
 145                         };
 146
 147                         xor@60900 {
 148                                 compatible = "marvell,armada-3700-xor";
 149                                 reg = <0x60900 0x100
 150                                        0x60b00 0x100>;
 151
 152                                 xor10 {
 153                                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 154                                 };
 155                                 xor11 {
 156                                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 157                                 };
 158                         };
 159
 160                         sata: sata@e0000 {
 161                                 compatible = "marvell,armada-3700-ahci";
 162                                 reg = <0xe0000 0x2000>;
 163                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 164                                 status = "disabled";
 165                         };
 166
 167                         gic: interrupt-controller@1d00000 {
 168                                 compatible = "arm,gic-v3";
 169                                 #interrupt-cells = <3>;
 170                                 interrupt-controller;
 171                                 reg = <0x1d00000 0x10000>, /* GICD */
 172                                       <0x1d40000 0x40000>; /* GICR */
 173                                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 174                         };
 175                 };
 176
 177                 pcie0: pcie@d0070000 {
 178                         compatible = "marvell,armada-3700-pcie";
 179                         device_type = "pci";
 180                         status = "disabled";
 181                         reg = <0 0xd0070000 0 0x20000>;
 182                         #address-cells = <3>;
 183                         #size-cells = <2>;
 184                         bus-range = <0x00 0xff>;
 185                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 186                         #interrupt-cells = <1>;
 187                         msi-parent = <&pcie0>;
 188                         msi-controller;
 189                         /*
 190                          * The 128 MiB address range [0xe8000000-0xf0000000] is
 191                          * dedicated for PCIe and can be assigned to 8 windows
 192                          * with size a power of two. Use one 64 KiB window for
 193                          * IO at the end and the remaining seven windows
 194                          * (totaling 127 MiB) for MEM.
 195                          */
 196                         ranges = <0x82000000 0 0xe8000000   0 0xe8000000   0 0x07f00000   /* Port 0 MEM */
 197                                   0x81000000 0 0xefff0000   0 0xefff0000   0 0x00010000>; /* Port 0 IO */
 198                         interrupt-map-mask = <0 0 0 7>;
 199                         interrupt-map = <0 0 0 1 &pcie_intc 0>,
 200                                         <0 0 0 2 &pcie_intc 1>,
 201                                         <0 0 0 3 &pcie_intc 2>,
 202                                         <0 0 0 4 &pcie_intc 3>;
 203                         pcie_intc: interrupt-controller {
 204                                 interrupt-controller;
 205                                 #interrupt-cells = <1>;
 206                         };
 207                 };
 208         };
 209 };