1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for CZ.NIC Turris Mox Board
4 * 2019 by Marek BehĂșn <kabel@kernel.org>
9 #include <dt-bindings/bus/moxtet.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include "armada-372x.dtsi"
15 model = "CZ.NIC Turris Mox Board";
16 compatible = "cznic,turris-mox", "marvell,armada3720",
28 stdout-path = "serial0:115200n8";
32 device_type = "memory";
33 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
37 compatible = "gpio-leds";
39 label = "mox:red:activity";
40 gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
41 linux,default-trigger = "default-on";
46 compatible = "gpio-keys";
50 linux,code = <KEY_RESTART>;
51 gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
52 debounce-interval = <60>;
56 exp_usb3_vbus: usb3-vbus {
57 compatible = "regulator-fixed";
58 regulator-name = "usb3-vbus";
59 regulator-min-microvolt = <5000000>;
60 regulator-max-microvolt = <5000000>;
63 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
67 compatible = "regulator-gpio";
68 regulator-name = "vsdc";
69 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <3300000>;
73 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
80 vsdio_reg: vsdio-reg {
81 compatible = "regulator-gpio";
82 regulator-name = "vsdio";
83 regulator-min-microvolt = <1800000>;
84 regulator-max-microvolt = <3300000>;
87 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
94 sdhci1_pwrseq: sdhci1-pwrseq {
95 compatible = "mmc-pwrseq-simple";
96 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
101 compatible = "sff,sfp";
103 los-gpios = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
104 tx-fault-gpios = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
105 mod-def0-gpios = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
106 tx-disable-gpios = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
107 rate-select0-gpios = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
108 maximum-power-milliwatt = <3000>;
110 /* enabled by U-Boot if SFP module is present */
116 compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
122 pinctrl-names = "default";
123 pinctrl-0 = <&i2c1_pins>;
124 clock-frequency = <100000>;
125 /delete-property/ mrvl,i2c-fast-mode;
128 /* MCP7940MT-I/MNY RTC */
130 compatible = "microchip,mcp7940x";
132 interrupt-parent = <&gpiosb>;
133 interrupts = <5 0>; /* GPIO2_5 */
138 pinctrl-names = "default";
139 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
141 reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
142 slot-power-limit-milliwatt = <10000>;
144 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
145 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
146 * 2 size cells and also expects that the second range starts at 16 MB offset. Also it
147 * expects that first range uses same address for PCI (child) and CPU (parent) cells (so
148 * no remapping) and that this address is the lowest from all specified ranges. If these
149 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
150 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
151 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
152 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
153 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
154 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
155 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
156 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
157 * Bug related to requirement of same child and parent addresses for first range is fixed
158 * in U-Boot version 2022.04 by following commit:
159 * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17
161 #address-cells = <3>;
163 ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */
164 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */
166 /* enabled by U-Boot if PCIe module is present */
175 pinctrl-names = "default";
176 pinctrl-0 = <&rgmii_pins>;
177 phy-mode = "rgmii-id";
178 phy-handle = <&phy1>;
183 phy-mode = "2500base-x";
184 managed = "in-band-status";
191 cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
192 vqmmc-supply = <&vsdc_reg>;
193 marvell,pad-type = "sd";
198 pinctrl-names = "default";
199 pinctrl-0 = <&sdio_pins>;
202 marvell,pad-type = "sd";
203 vqmmc-supply = <&vsdio_reg>;
204 mmc-pwrseq = <&sdhci1_pwrseq>;
205 /* forbid SDR104 for FCC purposes */
206 sdhci-caps-mask = <0x2 0x0>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
214 assigned-clocks = <&nb_periph_clk 7>;
215 assigned-clock-parents = <&tbg 1>;
216 assigned-clock-rates = <20000000>;
219 #address-cells = <1>;
221 compatible = "jedec,spi-nor";
223 spi-max-frequency = <20000000>;
226 compatible = "fixed-partitions";
227 #address-cells = <1>;
231 label = "secure-firmware";
236 label = "a53-firmware";
237 reg = <0x20000 0x160000>;
241 label = "u-boot-env";
242 reg = <0x180000 0x10000>;
246 label = "Rescue system";
247 reg = <0x190000 0x660000>;
252 reg = <0x7f0000 0x10000>;
258 #address-cells = <1>;
260 compatible = "cznic,moxtet";
262 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
263 spi-max-frequency = <10000000>;
266 interrupt-controller;
267 #interrupt-cells = <1>;
268 interrupt-parent = <&gpiosb>;
269 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
273 compatible = "cznic,moxtet-gpio";
288 compatible = "usb-a-connector";
289 phy-supply = <&exp_usb3_vbus>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&smi_pins>;
303 phy1: ethernet-phy@1 {
307 /* switch nodes are enabled by U-Boot if modules are present */
309 compatible = "marvell,mv88e6190";
312 interrupt-parent = <&moxtet>;
313 interrupts = <MOXTET_IRQ_PERIDOT(0)>;
317 #address-cells = <1>;
320 switch0phy1: switch0phy1@1 {
324 switch0phy2: switch0phy2@2 {
328 switch0phy3: switch0phy3@3 {
332 switch0phy4: switch0phy4@4 {
336 switch0phy5: switch0phy5@5 {
340 switch0phy6: switch0phy6@6 {
344 switch0phy7: switch0phy7@7 {
348 switch0phy8: switch0phy8@8 {
354 #address-cells = <1>;
360 phy-handle = <&switch0phy1>;
366 phy-handle = <&switch0phy2>;
372 phy-handle = <&switch0phy3>;
378 phy-handle = <&switch0phy4>;
384 phy-handle = <&switch0phy5>;
390 phy-handle = <&switch0phy6>;
396 phy-handle = <&switch0phy7>;
402 phy-handle = <&switch0phy8>;
409 phy-mode = "2500base-x";
410 managed = "in-band-status";
413 switch0port10: port@a {
416 phy-mode = "2500base-x";
417 managed = "in-band-status";
418 link = <&switch1port9 &switch2port9>;
427 managed = "in-band-status";
434 compatible = "marvell,mv88e6085";
437 interrupt-parent = <&moxtet>;
438 interrupts = <MOXTET_IRQ_TOPAZ>;
442 #address-cells = <1>;
445 switch0phy1_topaz: switch0phy1@11 {
449 switch0phy2_topaz: switch0phy2@12 {
453 switch0phy3_topaz: switch0phy3@13 {
457 switch0phy4_topaz: switch0phy4@14 {
463 #address-cells = <1>;
469 phy-handle = <&switch0phy1_topaz>;
475 phy-handle = <&switch0phy2_topaz>;
481 phy-handle = <&switch0phy3_topaz>;
487 phy-handle = <&switch0phy4_topaz>;
493 phy-mode = "2500base-x";
494 managed = "in-band-status";
501 compatible = "marvell,mv88e6190";
504 interrupt-parent = <&moxtet>;
505 interrupts = <MOXTET_IRQ_PERIDOT(1)>;
509 #address-cells = <1>;
512 switch1phy1: switch1phy1@1 {
516 switch1phy2: switch1phy2@2 {
520 switch1phy3: switch1phy3@3 {
524 switch1phy4: switch1phy4@4 {
528 switch1phy5: switch1phy5@5 {
532 switch1phy6: switch1phy6@6 {
536 switch1phy7: switch1phy7@7 {
540 switch1phy8: switch1phy8@8 {
546 #address-cells = <1>;
552 phy-handle = <&switch1phy1>;
558 phy-handle = <&switch1phy2>;
564 phy-handle = <&switch1phy3>;
570 phy-handle = <&switch1phy4>;
576 phy-handle = <&switch1phy5>;
582 phy-handle = <&switch1phy6>;
588 phy-handle = <&switch1phy7>;
594 phy-handle = <&switch1phy8>;
597 switch1port9: port@9 {
600 phy-mode = "2500base-x";
601 managed = "in-band-status";
602 link = <&switch0port10>;
605 switch1port10: port@a {
608 phy-mode = "2500base-x";
609 managed = "in-band-status";
610 link = <&switch2port9>;
619 managed = "in-band-status";
626 compatible = "marvell,mv88e6085";
629 interrupt-parent = <&moxtet>;
630 interrupts = <MOXTET_IRQ_TOPAZ>;
634 #address-cells = <1>;
637 switch1phy1_topaz: switch1phy1@11 {
641 switch1phy2_topaz: switch1phy2@12 {
645 switch1phy3_topaz: switch1phy3@13 {
649 switch1phy4_topaz: switch1phy4@14 {
655 #address-cells = <1>;
661 phy-handle = <&switch1phy1_topaz>;
667 phy-handle = <&switch1phy2_topaz>;
673 phy-handle = <&switch1phy3_topaz>;
679 phy-handle = <&switch1phy4_topaz>;
685 phy-mode = "2500base-x";
686 managed = "in-band-status";
687 link = <&switch0port10>;
693 compatible = "marvell,mv88e6190";
696 interrupt-parent = <&moxtet>;
697 interrupts = <MOXTET_IRQ_PERIDOT(2)>;
701 #address-cells = <1>;
704 switch2phy1: switch2phy1@1 {
708 switch2phy2: switch2phy2@2 {
712 switch2phy3: switch2phy3@3 {
716 switch2phy4: switch2phy4@4 {
720 switch2phy5: switch2phy5@5 {
724 switch2phy6: switch2phy6@6 {
728 switch2phy7: switch2phy7@7 {
732 switch2phy8: switch2phy8@8 {
738 #address-cells = <1>;
744 phy-handle = <&switch2phy1>;
750 phy-handle = <&switch2phy2>;
756 phy-handle = <&switch2phy3>;
762 phy-handle = <&switch2phy4>;
768 phy-handle = <&switch2phy5>;
774 phy-handle = <&switch2phy6>;
780 phy-handle = <&switch2phy7>;
786 phy-handle = <&switch2phy8>;
789 switch2port9: port@9 {
792 phy-mode = "2500base-x";
793 managed = "in-band-status";
794 link = <&switch1port10 &switch0port10>;
802 managed = "in-band-status";
809 compatible = "marvell,mv88e6085";
812 interrupt-parent = <&moxtet>;
813 interrupts = <MOXTET_IRQ_TOPAZ>;
817 #address-cells = <1>;
820 switch2phy1_topaz: switch2phy1@11 {
824 switch2phy2_topaz: switch2phy2@12 {
828 switch2phy3_topaz: switch2phy3@13 {
832 switch2phy4_topaz: switch2phy4@14 {
838 #address-cells = <1>;
844 phy-handle = <&switch2phy1_topaz>;
850 phy-handle = <&switch2phy2_topaz>;
856 phy-handle = <&switch2phy3_topaz>;
862 phy-handle = <&switch2phy4_topaz>;
868 phy-mode = "2500base-x";
869 managed = "in-band-status";
870 link = <&switch1port10 &switch0port10>;