arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree file for CZ.NIC Turris Mox Board
   4  * 2019 by Marek Behún <kabel@kernel.org>
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/bus/moxtet.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12 #include "armada-372x.dtsi"
  13
  14 / {
  15         model = "CZ.NIC Turris Mox Board";
  16         compatible = "cznic,turris-mox", "marvell,armada3720",
  17                      "marvell,armada3710";
  18
  19         aliases {
  20                 spi0 = &spi0;
  21                 ethernet0 = &eth0;
  22                 ethernet1 = &eth1;
  23                 mmc0 = &sdhci0;
  24                 mmc1 = &sdhci1;
  25         };
  26
  27         chosen {
  28                 stdout-path = "serial0:115200n8";
  29         };
  30
  31         memory@0 {
  32                 device_type = "memory";
  33                 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
  34         };
  35
  36         leds {
  37                 compatible = "gpio-leds";
  38                 led {
  39                         label = "mox:red:activity";
  40                         gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
  41                         linux,default-trigger = "default-on";
  42                 };
  43         };
  44
  45         gpio-keys {
  46                 compatible = "gpio-keys";
  47
  48                 key-reset {
  49                         label = "reset";
  50                         linux,code = <KEY_RESTART>;
  51                         gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
  52                         debounce-interval = <60>;
  53                 };
  54         };
  55
  56         exp_usb3_vbus: usb3-vbus {
  57                 compatible = "regulator-fixed";
  58                 regulator-name = "usb3-vbus";
  59                 regulator-min-microvolt = <5000000>;
  60                 regulator-max-microvolt = <5000000>;
  61                 enable-active-high;
  62                 regulator-always-on;
  63                 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
  64         };
  65
  66         vsdc_reg: vsdc-reg {
  67                 compatible = "regulator-gpio";
  68                 regulator-name = "vsdc";
  69                 regulator-min-microvolt = <1800000>;
  70                 regulator-max-microvolt = <3300000>;
  71                 regulator-boot-on;
  72
  73                 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
  74                 gpios-states = <0>;
  75                 states = <1800000 0x1
  76                           3300000 0x0>;
  77                 enable-active-high;
  78         };
  79
  80         vsdio_reg: vsdio-reg {
  81                 compatible = "regulator-gpio";
  82                 regulator-name = "vsdio";
  83                 regulator-min-microvolt = <1800000>;
  84                 regulator-max-microvolt = <3300000>;
  85                 regulator-boot-on;
  86
  87                 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
  88                 gpios-states = <0>;
  89                 states = <1800000 0x1
  90                           3300000 0x0>;
  91                 enable-active-high;
  92         };
  93
  94         sdhci1_pwrseq: sdhci1-pwrseq {
  95                 compatible = "mmc-pwrseq-simple";
  96                 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
  97                 status = "okay";
  98         };
  99
 100         sfp: sfp {
 101                 compatible = "sff,sfp";
 102                 i2c-bus = <&i2c0>;
 103                 los-gpios = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
 104                 tx-fault-gpios = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
 105                 mod-def0-gpios = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
 106                 tx-disable-gpios = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
 107                 rate-select0-gpios = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
 108                 maximum-power-milliwatt = <3000>;
 109
 110                 /* enabled by U-Boot if SFP module is present */
 111                 status = "disabled";
 112         };
 113
 114         firmware {
 115                 armada-3700-rwtm {
 116                         compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
 117                 };
 118         };
 119 };
 120
 121 &i2c0 {
 122         pinctrl-names = "default";
 123         pinctrl-0 = <&i2c1_pins>;
 124         clock-frequency = <100000>;
 125         /delete-property/ mrvl,i2c-fast-mode;
 126         status = "okay";
 127
 128         /* MCP7940MT-I/MNY RTC */
 129         rtc@6f {
 130                 compatible = "microchip,mcp7940x";
 131                 reg = <0x6f>;
 132                 interrupt-parent = <&gpiosb>;
 133                 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO2_5 */
 134         };
 135 };
 136
 137 &pcie0 {
 138         pinctrl-names = "default";
 139         pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
 140         status = "okay";
 141         reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
 142         /*
 143          * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
 144          * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
 145          * 2 size cells and also expects that the second range starts at 16 MB offset. Also it
 146          * expects that first range uses same address for PCI (child) and CPU (parent) cells (so
 147          * no remapping) and that this address is the lowest from all specified ranges. If these
 148          * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
 149          * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
 150          * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
 151          * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
 152          * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
 153          * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
 154          * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
 155          * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
 156          * Bug related to requirement of same child and parent addresses for first range is fixed
 157          * in U-Boot version 2022.04 by following commit:
 158          * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17
 159          */
 160         #address-cells = <3>;
 161         #size-cells = <2>;
 162         ranges = <0x81000000 0 0xe8000000   0 0xe8000000   0 0x01000000   /* Port 0 IO */
 163                   0x82000000 0 0xe9000000   0 0xe9000000   0 0x07000000>; /* Port 0 MEM */
 164
 165         /* enabled by U-Boot if PCIe module is present */
 166         status = "disabled";
 167 };
 168
 169 &uart0 {
 170         status = "okay";
 171 };
 172
 173 &eth0 {
 174         pinctrl-names = "default";
 175         pinctrl-0 = <&rgmii_pins>;
 176         phy-mode = "rgmii-id";
 177         phy-handle = <&phy1>;
 178         status = "okay";
 179 };
 180
 181 &eth1 {
 182         phy-mode = "2500base-x";
 183         managed = "in-band-status";
 184         phys = <&comphy0 1>;
 185 };
 186
 187 &sdhci0 {
 188         wp-inverted;
 189         bus-width = <4>;
 190         cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
 191         vqmmc-supply = <&vsdc_reg>;
 192         marvell,pad-type = "sd";
 193         status = "okay";
 194 };
 195
 196 &sdhci1 {
 197         pinctrl-names = "default";
 198         pinctrl-0 = <&sdio_pins>;
 199         non-removable;
 200         bus-width = <4>;
 201         marvell,pad-type = "sd";
 202         vqmmc-supply = <&vsdio_reg>;
 203         mmc-pwrseq = <&sdhci1_pwrseq>;
 204         /* forbid SDR104 for FCC purposes */
 205         sdhci-caps-mask = <0x2 0x0>;
 206         status = "okay";
 207 };
 208
 209 &spi0 {
 210         status = "okay";
 211         pinctrl-names = "default";
 212         pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
 213         assigned-clocks = <&nb_periph_clk 7>;
 214         assigned-clock-parents = <&tbg 1>;
 215         assigned-clock-rates = <20000000>;
 216
 217         flash@0 {
 218                 #address-cells = <1>;
 219                 #size-cells = <1>;
 220                 compatible = "jedec,spi-nor";
 221                 reg = <0>;
 222                 spi-max-frequency = <20000000>;
 223
 224                 partitions {
 225                         compatible = "fixed-partitions";
 226                         #address-cells = <1>;
 227                         #size-cells = <1>;
 228
 229                         partition@0 {
 230                                 label = "secure-firmware";
 231                                 reg = <0x0 0x20000>;
 232                         };
 233
 234                         partition@20000 {
 235                                 label = "a53-firmware";
 236                                 reg = <0x20000 0x160000>;
 237                         };
 238
 239                         partition@180000 {
 240                                 label = "u-boot-env";
 241                                 reg = <0x180000 0x10000>;
 242                         };
 243
 244                         partition@190000 {
 245                                 label = "Rescue system";
 246                                 reg = <0x190000 0x660000>;
 247                         };
 248
 249                         partition@7f0000 {
 250                                 label = "dtb";
 251                                 reg = <0x7f0000 0x10000>;
 252                         };
 253                 };
 254         };
 255
 256         moxtet: moxtet@1 {
 257                 #address-cells = <1>;
 258                 #size-cells = <0>;
 259                 compatible = "cznic,moxtet";
 260                 reg = <1>;
 261                 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
 262                 spi-max-frequency = <10000000>;
 263                 spi-cpol;
 264                 spi-cpha;
 265                 interrupt-controller;
 266                 #interrupt-cells = <1>;
 267                 interrupt-parent = <&gpiosb>;
 268                 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
 269                 status = "okay";
 270
 271                 moxtet_sfp: gpio@0 {
 272                         compatible = "cznic,moxtet-gpio";
 273                         gpio-controller;
 274                         #gpio-cells = <2>;
 275                         reg = <0>;
 276                         status = "disabled";
 277                 };
 278         };
 279 };
 280
 281 &usb2 {
 282         status = "okay";
 283 };
 284
 285 &comphy2 {
 286         connector {
 287                 compatible = "usb-a-connector";
 288                 phy-supply = <&exp_usb3_vbus>;
 289         };
 290 };
 291
 292 &usb3 {
 293         status = "okay";
 294         phys = <&comphy2 0>;
 295 };
 296
 297 &mdio {
 298         pinctrl-names = "default";
 299         pinctrl-0 = <&smi_pins>;
 300         status = "okay";
 301
 302         phy1: ethernet-phy@1 {
 303                 reg = <1>;
 304         };
 305
 306         /* switch nodes are enabled by U-Boot if modules are present */
 307         switch0@10 {
 308                 compatible = "marvell,mv88e6190";
 309                 reg = <0x10>;
 310                 dsa,member = <0 0>;
 311                 interrupt-parent = <&moxtet>;
 312                 interrupts = <MOXTET_IRQ_PERIDOT(0)>;
 313                 status = "disabled";
 314
 315                 mdio {
 316                         #address-cells = <1>;
 317                         #size-cells = <0>;
 318
 319                         switch0phy1: switch0phy1@1 {
 320                                 reg = <0x1>;
 321                         };
 322
 323                         switch0phy2: switch0phy2@2 {
 324                                 reg = <0x2>;
 325                         };
 326
 327                         switch0phy3: switch0phy3@3 {
 328                                 reg = <0x3>;
 329                         };
 330
 331                         switch0phy4: switch0phy4@4 {
 332                                 reg = <0x4>;
 333                         };
 334
 335                         switch0phy5: switch0phy5@5 {
 336                                 reg = <0x5>;
 337                         };
 338
 339                         switch0phy6: switch0phy6@6 {
 340                                 reg = <0x6>;
 341                         };
 342
 343                         switch0phy7: switch0phy7@7 {
 344                                 reg = <0x7>;
 345                         };
 346
 347                         switch0phy8: switch0phy8@8 {
 348                                 reg = <0x8>;
 349                         };
 350                 };
 351
 352                 ports {
 353                         #address-cells = <1>;
 354                         #size-cells = <0>;
 355
 356                         port@1 {
 357                                 reg = <0x1>;
 358                                 label = "lan1";
 359                                 phy-handle = <&switch0phy1>;
 360                         };
 361
 362                         port@2 {
 363                                 reg = <0x2>;
 364                                 label = "lan2";
 365                                 phy-handle = <&switch0phy2>;
 366                         };
 367
 368                         port@3 {
 369                                 reg = <0x3>;
 370                                 label = "lan3";
 371                                 phy-handle = <&switch0phy3>;
 372                         };
 373
 374                         port@4 {
 375                                 reg = <0x4>;
 376                                 label = "lan4";
 377                                 phy-handle = <&switch0phy4>;
 378                         };
 379
 380                         port@5 {
 381                                 reg = <0x5>;
 382                                 label = "lan5";
 383                                 phy-handle = <&switch0phy5>;
 384                         };
 385
 386                         port@6 {
 387                                 reg = <0x6>;
 388                                 label = "lan6";
 389                                 phy-handle = <&switch0phy6>;
 390                         };
 391
 392                         port@7 {
 393                                 reg = <0x7>;
 394                                 label = "lan7";
 395                                 phy-handle = <&switch0phy7>;
 396                         };
 397
 398                         port@8 {
 399                                 reg = <0x8>;
 400                                 label = "lan8";
 401                                 phy-handle = <&switch0phy8>;
 402                         };
 403
 404                         port@9 {
 405                                 reg = <0x9>;
 406                                 label = "cpu";
 407                                 ethernet = <&eth1>;
 408                                 phy-mode = "2500base-x";
 409                                 managed = "in-band-status";
 410                         };
 411
 412                         switch0port10: port@a {
 413                                 reg = <0xa>;
 414                                 label = "dsa";
 415                                 phy-mode = "2500base-x";
 416                                 managed = "in-band-status";
 417                                 link = <&switch1port9 &switch2port9>;
 418                                 status = "disabled";
 419                         };
 420
 421                         port-sfp@a {
 422                                 reg = <0xa>;
 423                                 label = "sfp";
 424                                 sfp = <&sfp>;
 425                                 phy-mode = "sgmii";
 426                                 managed = "in-band-status";
 427                                 status = "disabled";
 428                         };
 429                 };
 430         };
 431
 432         switch0@2 {
 433                 compatible = "marvell,mv88e6085";
 434                 reg = <0x2>;
 435                 dsa,member = <0 0>;
 436                 interrupt-parent = <&moxtet>;
 437                 interrupts = <MOXTET_IRQ_TOPAZ>;
 438                 status = "disabled";
 439
 440                 mdio {
 441                         #address-cells = <1>;
 442                         #size-cells = <0>;
 443
 444                         switch0phy1_topaz: switch0phy1@11 {
 445                                 reg = <0x11>;
 446                         };
 447
 448                         switch0phy2_topaz: switch0phy2@12 {
 449                                 reg = <0x12>;
 450                         };
 451
 452                         switch0phy3_topaz: switch0phy3@13 {
 453                                 reg = <0x13>;
 454                         };
 455
 456                         switch0phy4_topaz: switch0phy4@14 {
 457                                 reg = <0x14>;
 458                         };
 459                 };
 460
 461                 ports {
 462                         #address-cells = <1>;
 463                         #size-cells = <0>;
 464
 465                         port@1 {
 466                                 reg = <0x1>;
 467                                 label = "lan1";
 468                                 phy-handle = <&switch0phy1_topaz>;
 469                         };
 470
 471                         port@2 {
 472                                 reg = <0x2>;
 473                                 label = "lan2";
 474                                 phy-handle = <&switch0phy2_topaz>;
 475                         };
 476
 477                         port@3 {
 478                                 reg = <0x3>;
 479                                 label = "lan3";
 480                                 phy-handle = <&switch0phy3_topaz>;
 481                         };
 482
 483                         port@4 {
 484                                 reg = <0x4>;
 485                                 label = "lan4";
 486                                 phy-handle = <&switch0phy4_topaz>;
 487                         };
 488
 489                         port@5 {
 490                                 reg = <0x5>;
 491                                 label = "cpu";
 492                                 phy-mode = "2500base-x";
 493                                 managed = "in-band-status";
 494                                 ethernet = <&eth1>;
 495                         };
 496                 };
 497         };
 498
 499         switch1@11 {
 500                 compatible = "marvell,mv88e6190";
 501                 reg = <0x11>;
 502                 dsa,member = <0 1>;
 503                 interrupt-parent = <&moxtet>;
 504                 interrupts = <MOXTET_IRQ_PERIDOT(1)>;
 505                 status = "disabled";
 506
 507                 mdio {
 508                         #address-cells = <1>;
 509                         #size-cells = <0>;
 510
 511                         switch1phy1: switch1phy1@1 {
 512                                 reg = <0x1>;
 513                         };
 514
 515                         switch1phy2: switch1phy2@2 {
 516                                 reg = <0x2>;
 517                         };
 518
 519                         switch1phy3: switch1phy3@3 {
 520                                 reg = <0x3>;
 521                         };
 522
 523                         switch1phy4: switch1phy4@4 {
 524                                 reg = <0x4>;
 525                         };
 526
 527                         switch1phy5: switch1phy5@5 {
 528                                 reg = <0x5>;
 529                         };
 530
 531                         switch1phy6: switch1phy6@6 {
 532                                 reg = <0x6>;
 533                         };
 534
 535                         switch1phy7: switch1phy7@7 {
 536                                 reg = <0x7>;
 537                         };
 538
 539                         switch1phy8: switch1phy8@8 {
 540                                 reg = <0x8>;
 541                         };
 542                 };
 543
 544                 ports {
 545                         #address-cells = <1>;
 546                         #size-cells = <0>;
 547
 548                         port@1 {
 549                                 reg = <0x1>;
 550                                 label = "lan9";
 551                                 phy-handle = <&switch1phy1>;
 552                         };
 553
 554                         port@2 {
 555                                 reg = <0x2>;
 556                                 label = "lan10";
 557                                 phy-handle = <&switch1phy2>;
 558                         };
 559
 560                         port@3 {
 561                                 reg = <0x3>;
 562                                 label = "lan11";
 563                                 phy-handle = <&switch1phy3>;
 564                         };
 565
 566                         port@4 {
 567                                 reg = <0x4>;
 568                                 label = "lan12";
 569                                 phy-handle = <&switch1phy4>;
 570                         };
 571
 572                         port@5 {
 573                                 reg = <0x5>;
 574                                 label = "lan13";
 575                                 phy-handle = <&switch1phy5>;
 576                         };
 577
 578                         port@6 {
 579                                 reg = <0x6>;
 580                                 label = "lan14";
 581                                 phy-handle = <&switch1phy6>;
 582                         };
 583
 584                         port@7 {
 585                                 reg = <0x7>;
 586                                 label = "lan15";
 587                                 phy-handle = <&switch1phy7>;
 588                         };
 589
 590                         port@8 {
 591                                 reg = <0x8>;
 592                                 label = "lan16";
 593                                 phy-handle = <&switch1phy8>;
 594                         };
 595
 596                         switch1port9: port@9 {
 597                                 reg = <0x9>;
 598                                 label = "dsa";
 599                                 phy-mode = "2500base-x";
 600                                 managed = "in-band-status";
 601                                 link = <&switch0port10>;
 602                         };
 603
 604                         switch1port10: port@a {
 605                                 reg = <0xa>;
 606                                 label = "dsa";
 607                                 phy-mode = "2500base-x";
 608                                 managed = "in-band-status";
 609                                 link = <&switch2port9>;
 610                                 status = "disabled";
 611                         };
 612
 613                         port-sfp@a {
 614                                 reg = <0xa>;
 615                                 label = "sfp";
 616                                 sfp = <&sfp>;
 617                                 phy-mode = "sgmii";
 618                                 managed = "in-band-status";
 619                                 status = "disabled";
 620                         };
 621                 };
 622         };
 623
 624         switch1@2 {
 625                 compatible = "marvell,mv88e6085";
 626                 reg = <0x2>;
 627                 dsa,member = <0 1>;
 628                 interrupt-parent = <&moxtet>;
 629                 interrupts = <MOXTET_IRQ_TOPAZ>;
 630                 status = "disabled";
 631
 632                 mdio {
 633                         #address-cells = <1>;
 634                         #size-cells = <0>;
 635
 636                         switch1phy1_topaz: switch1phy1@11 {
 637                                 reg = <0x11>;
 638                         };
 639
 640                         switch1phy2_topaz: switch1phy2@12 {
 641                                 reg = <0x12>;
 642                         };
 643
 644                         switch1phy3_topaz: switch1phy3@13 {
 645                                 reg = <0x13>;
 646                         };
 647
 648                         switch1phy4_topaz: switch1phy4@14 {
 649                                 reg = <0x14>;
 650                         };
 651                 };
 652
 653                 ports {
 654                         #address-cells = <1>;
 655                         #size-cells = <0>;
 656
 657                         port@1 {
 658                                 reg = <0x1>;
 659                                 label = "lan9";
 660                                 phy-handle = <&switch1phy1_topaz>;
 661                         };
 662
 663                         port@2 {
 664                                 reg = <0x2>;
 665                                 label = "lan10";
 666                                 phy-handle = <&switch1phy2_topaz>;
 667                         };
 668
 669                         port@3 {
 670                                 reg = <0x3>;
 671                                 label = "lan11";
 672                                 phy-handle = <&switch1phy3_topaz>;
 673                         };
 674
 675                         port@4 {
 676                                 reg = <0x4>;
 677                                 label = "lan12";
 678                                 phy-handle = <&switch1phy4_topaz>;
 679                         };
 680
 681                         port@5 {
 682                                 reg = <0x5>;
 683                                 label = "dsa";
 684                                 phy-mode = "2500base-x";
 685                                 managed = "in-band-status";
 686                                 link = <&switch0port10>;
 687                         };
 688                 };
 689         };
 690
 691         switch2@12 {
 692                 compatible = "marvell,mv88e6190";
 693                 reg = <0x12>;
 694                 dsa,member = <0 2>;
 695                 interrupt-parent = <&moxtet>;
 696                 interrupts = <MOXTET_IRQ_PERIDOT(2)>;
 697                 status = "disabled";
 698
 699                 mdio {
 700                         #address-cells = <1>;
 701                         #size-cells = <0>;
 702
 703                         switch2phy1: switch2phy1@1 {
 704                                 reg = <0x1>;
 705                         };
 706
 707                         switch2phy2: switch2phy2@2 {
 708                                 reg = <0x2>;
 709                         };
 710
 711                         switch2phy3: switch2phy3@3 {
 712                                 reg = <0x3>;
 713                         };
 714
 715                         switch2phy4: switch2phy4@4 {
 716                                 reg = <0x4>;
 717                         };
 718
 719                         switch2phy5: switch2phy5@5 {
 720                                 reg = <0x5>;
 721                         };
 722
 723                         switch2phy6: switch2phy6@6 {
 724                                 reg = <0x6>;
 725                         };
 726
 727                         switch2phy7: switch2phy7@7 {
 728                                 reg = <0x7>;
 729                         };
 730
 731                         switch2phy8: switch2phy8@8 {
 732                                 reg = <0x8>;
 733                         };
 734                 };
 735
 736                 ports {
 737                         #address-cells = <1>;
 738                         #size-cells = <0>;
 739
 740                         port@1 {
 741                                 reg = <0x1>;
 742                                 label = "lan17";
 743                                 phy-handle = <&switch2phy1>;
 744                         };
 745
 746                         port@2 {
 747                                 reg = <0x2>;
 748                                 label = "lan18";
 749                                 phy-handle = <&switch2phy2>;
 750                         };
 751
 752                         port@3 {
 753                                 reg = <0x3>;
 754                                 label = "lan19";
 755                                 phy-handle = <&switch2phy3>;
 756                         };
 757
 758                         port@4 {
 759                                 reg = <0x4>;
 760                                 label = "lan20";
 761                                 phy-handle = <&switch2phy4>;
 762                         };
 763
 764                         port@5 {
 765                                 reg = <0x5>;
 766                                 label = "lan21";
 767                                 phy-handle = <&switch2phy5>;
 768                         };
 769
 770                         port@6 {
 771                                 reg = <0x6>;
 772                                 label = "lan22";
 773                                 phy-handle = <&switch2phy6>;
 774                         };
 775
 776                         port@7 {
 777                                 reg = <0x7>;
 778                                 label = "lan23";
 779                                 phy-handle = <&switch2phy7>;
 780                         };
 781
 782                         port@8 {
 783                                 reg = <0x8>;
 784                                 label = "lan24";
 785                                 phy-handle = <&switch2phy8>;
 786                         };
 787
 788                         switch2port9: port@9 {
 789                                 reg = <0x9>;
 790                                 label = "dsa";
 791                                 phy-mode = "2500base-x";
 792                                 managed = "in-band-status";
 793                                 link = <&switch1port10 &switch0port10>;
 794                         };
 795
 796                         port-sfp@a {
 797                                 reg = <0xa>;
 798                                 label = "sfp";
 799                                 sfp = <&sfp>;
 800                                 phy-mode = "sgmii";
 801                                 managed = "in-band-status";
 802                                 status = "disabled";
 803                         };
 804                 };
 805         };
 806
 807         switch2@2 {
 808                 compatible = "marvell,mv88e6085";
 809                 reg = <0x2>;
 810                 dsa,member = <0 2>;
 811                 interrupt-parent = <&moxtet>;
 812                 interrupts = <MOXTET_IRQ_TOPAZ>;
 813                 status = "disabled";
 814
 815                 mdio {
 816                         #address-cells = <1>;
 817                         #size-cells = <0>;
 818
 819                         switch2phy1_topaz: switch2phy1@11 {
 820                                 reg = <0x11>;
 821                         };
 822
 823                         switch2phy2_topaz: switch2phy2@12 {
 824                                 reg = <0x12>;
 825                         };
 826
 827                         switch2phy3_topaz: switch2phy3@13 {
 828                                 reg = <0x13>;
 829                         };
 830
 831                         switch2phy4_topaz: switch2phy4@14 {
 832                                 reg = <0x14>;
 833                         };
 834                 };
 835
 836                 ports {
 837                         #address-cells = <1>;
 838                         #size-cells = <0>;
 839
 840                         port@1 {
 841                                 reg = <0x1>;
 842                                 label = "lan17";
 843                                 phy-handle = <&switch2phy1_topaz>;
 844                         };
 845
 846                         port@2 {
 847                                 reg = <0x2>;
 848                                 label = "lan18";
 849                                 phy-handle = <&switch2phy2_topaz>;
 850                         };
 851
 852                         port@3 {
 853                                 reg = <0x3>;
 854                                 label = "lan19";
 855                                 phy-handle = <&switch2phy3_topaz>;
 856                         };
 857
 858                         port@4 {
 859                                 reg = <0x4>;
 860                                 label = "lan20";
 861                                 phy-handle = <&switch2phy4_topaz>;
 862                         };
 863
 864                         port@5 {
 865                                 reg = <0x5>;
 866                                 label = "dsa";
 867                                 phy-mode = "2500base-x";
 868                                 managed = "in-band-status";
 869                                 link = <&switch1port10 &switch0port10>;
 870                         };
 871                 };
 872         };
 873 };