1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright (C) 2021 Marvell
6 * Copyright (C) 2022 Allied Telesis Labs
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 model = "Marvell AC5 SoC";
14 compatible = "marvell,ac5";
15 interrupt-parent = <&gic>;
36 compatible = "arm,cortex-a55";
38 enable-method = "psci";
39 next-level-cache = <&l2>;
44 compatible = "arm,cortex-a55";
46 enable-method = "psci";
47 next-level-cache = <&l2>;
58 compatible = "arm,psci-0.2";
63 compatible = "arm,armv8-timer";
64 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
71 compatible = "arm,armv8-pmuv3";
72 interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
76 compatible = "simple-bus";
82 internal-regs@7f000000 {
85 compatible = "simple-bus";
86 /* 16M internal register @ 0x7f00_0000 */
87 ranges = <0x0 0x0 0x7f000000 0x1000000>;
91 compatible = "snps,dw-apb-uart";
92 reg = <0x12000 0x100>;
94 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
96 clocks = <&cnm_clock>;
100 uart1: serial@12100 {
101 compatible = "snps,dw-apb-uart";
102 reg = <0x12100 0x100>;
104 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
106 clocks = <&cnm_clock>;
110 uart2: serial@12200 {
111 compatible = "snps,dw-apb-uart";
112 reg = <0x12200 0x100>;
114 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&cnm_clock>;
120 uart3: serial@12300 {
121 compatible = "snps,dw-apb-uart";
122 reg = <0x12300 0x100>;
124 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
126 clocks = <&cnm_clock>;
131 #address-cells = <1>;
133 compatible = "marvell,orion-mdio";
135 clocks = <&cnm_clock>;
139 compatible = "marvell,mv78230-i2c";
140 reg = <0x11000 0x20>;
141 #address-cells = <1>;
144 clocks = <&cnm_clock>;
145 clock-names = "core";
146 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
147 clock-frequency = <100000>;
149 pinctrl-names = "default", "gpio";
150 pinctrl-0 = <&i2c0_pins>;
151 pinctrl-1 = <&i2c0_gpio>;
152 scl-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
153 sda-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
158 compatible = "marvell,mv78230-i2c";
159 reg = <0x11100 0x20>;
160 #address-cells = <1>;
163 clocks = <&cnm_clock>;
164 clock-names = "core";
165 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
166 clock-frequency = <100000>;
168 pinctrl-names = "default", "gpio";
169 pinctrl-0 = <&i2c1_pins>;
170 pinctrl-1 = <&i2c1_gpio>;
171 scl-gpios = <&gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
172 sda-gpios = <&gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
177 compatible = "marvell,orion-gpio";
178 reg = <0x18100 0x40>;
182 gpio-ranges = <&pinctrl0 0 0 32>;
183 marvell,pwm-offset = <0x1f0>;
184 interrupt-controller;
185 #interrupt-cells = <2>;
186 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
193 reg = <0x18140 0x40>;
194 compatible = "marvell,orion-gpio";
198 gpio-ranges = <&pinctrl0 0 32 14>;
199 marvell,pwm-offset = <0x1f0>;
200 interrupt-controller;
201 #interrupt-cells = <2>;
202 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
208 * Dedicated section for devices behind 32bit controllers so we
209 * can configure specific DMA mapping for them
211 behind-32bit-controller@7f000000 {
212 compatible = "simple-bus";
213 #address-cells = <0x2>;
215 ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
216 /* Host phy ram starts at 0x200M */
217 dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
220 eth0: ethernet@20000 {
221 compatible = "marvell,armada-ac5-neta";
222 reg = <0x0 0x20000 0x0 0x4000>;
223 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&cnm_clock>;
229 eth1: ethernet@24000 {
230 compatible = "marvell,armada-ac5-neta";
231 reg = <0x0 0x24000 0x0 0x4000>;
232 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&cnm_clock>;
239 compatible = "marvell,orion-ehci";
240 reg = <0x0 0x80000 0x0 0x500>;
241 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
246 compatible = "marvell,orion-ehci";
247 reg = <0x0 0xa0000 0x0 0x500>;
248 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
253 pinctrl0: pinctrl@80020100 {
254 compatible = "marvell,ac5-pinctrl";
255 reg = <0 0x80020100 0 0x20>;
257 i2c0_pins: i2c0-pins {
258 marvell,pins = "mpp26", "mpp27";
259 marvell,function = "i2c0";
262 i2c0_gpio: i2c0-gpio-pins {
263 marvell,pins = "mpp26", "mpp27";
264 marvell,function = "gpio";
267 i2c1_pins: i2c1-pins {
268 marvell,pins = "mpp20", "mpp21";
269 marvell,function = "i2c1";
272 i2c1_gpio: i2c1-gpio-pins {
273 marvell,pins = "mpp20", "mpp21";
274 marvell,function = "i2c1";
279 compatible = "marvell,armada-3700-spi";
280 reg = <0x0 0x805a0000 0x0 0x50>;
281 #address-cells = <0x1>;
283 clocks = <&spi_clock>;
284 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
290 compatible = "marvell,armada-3700-spi";
291 reg = <0x0 0x805a8000 0x0 0x50>;
292 #address-cells = <0x1>;
294 clocks = <&spi_clock>;
295 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
300 nand: nand-controller@805b0000 {
301 compatible = "marvell,ac5-nand-controller";
302 reg = <0x0 0x805b0000 0x0 0x00000054>;
303 #address-cells = <0x1>;
305 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&nand_clock>;
310 gic: interrupt-controller@80600000 {
311 compatible = "arm,gic-v3";
312 #interrupt-cells = <3>;
313 interrupt-controller;
314 reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
315 <0x0 0x80660000 0x0 0x40000>; /* GICR */
316 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
321 cnm_clock: cnm-clock {
322 compatible = "fixed-clock";
324 clock-frequency = <328000000>;
327 spi_clock: spi-clock {
328 compatible = "fixed-clock";
330 clock-frequency = <200000000>;
333 nand_clock: nand-clock {
334 compatible = "fixed-clock";
336 clock-frequency = <400000000>;