arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree For AC5.
   4  *
   5  * Copyright (C) 2021 Marvell
   6  * Copyright (C) 2022 Allied Telesis Labs
   7  */
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 / {
  13         model = "Marvell AC5 SoC";
  14         compatible = "marvell,ac5";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         cpus {
  20                 #address-cells = <2>;
  21                 #size-cells = <0>;
  22
  23                 cpu-map {
  24                         cluster0 {
  25                                 core0 {
  26                                         cpu = <&cpu0>;
  27                                 };
  28                                 core1 {
  29                                         cpu = <&cpu1>;
  30                                 };
  31                         };
  32                 };
  33
  34                 cpu0: cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a55";
  37                         reg = <0x0 0x0>;
  38                         enable-method = "psci";
  39                         next-level-cache = <&l2>;
  40                 };
  41
  42                 cpu1: cpu@1 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a55";
  45                         reg = <0x0 0x100>;
  46                         enable-method = "psci";
  47                         next-level-cache = <&l2>;
  48                 };
  49
  50                 l2: l2-cache {
  51                         compatible = "cache";
  52                 };
  53         };
  54
  55         psci {
  56                 compatible = "arm,psci-0.2";
  57                 method = "smc";
  58         };
  59
  60         timer {
  61                 compatible = "arm,armv8-timer";
  62                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
  63                              <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
  64                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
  65                              <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
  66         };
  67
  68         pmu {
  69                 compatible = "arm,armv8-pmuv3";
  70                 interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
  71         };
  72
  73         soc {
  74                 compatible = "simple-bus";
  75                 #address-cells = <2>;
  76                 #size-cells = <2>;
  77                 ranges;
  78                 dma-ranges;
  79
  80                 internal-regs@7f000000 {
  81                         #address-cells = <1>;
  82                         #size-cells = <1>;
  83                         compatible = "simple-bus";
  84                         /* 16M internal register @ 0x7f00_0000 */
  85                         ranges = <0x0 0x0 0x7f000000 0x1000000>;
  86                         dma-coherent;
  87
  88                         uart0: serial@12000 {
  89                                 compatible = "snps,dw-apb-uart";
  90                                 reg = <0x12000 0x100>;
  91                                 reg-shift = <2>;
  92                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  93                                 reg-io-width = <1>;
  94                                 clocks = <&cnm_clock>;
  95                                 status = "okay";
  96                         };
  97
  98                         uart1: serial@12100 {
  99                                 compatible = "snps,dw-apb-uart";
 100                                 reg = <0x12100 0x100>;
 101                                 reg-shift = <2>;
 102                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 103                                 reg-io-width = <1>;
 104                                 clocks = <&cnm_clock>;
 105                                 status = "disabled";
 106                         };
 107
 108                         uart2: serial@12200 {
 109                                 compatible = "snps,dw-apb-uart";
 110                                 reg = <0x12200 0x100>;
 111                                 reg-shift = <2>;
 112                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 113                                 reg-io-width = <1>;
 114                                 clocks = <&cnm_clock>;
 115                                 status = "disabled";
 116                         };
 117
 118                         uart3: serial@12300 {
 119                                 compatible = "snps,dw-apb-uart";
 120                                 reg = <0x12300 0x100>;
 121                                 reg-shift = <2>;
 122                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 123                                 reg-io-width = <1>;
 124                                 clocks = <&cnm_clock>;
 125                                 status = "disabled";
 126                         };
 127
 128                         mdio: mdio@22004 {
 129                                 #address-cells = <1>;
 130                                 #size-cells = <0>;
 131                                 compatible = "marvell,orion-mdio";
 132                                 reg = <0x22004 0x4>;
 133                                 clocks = <&cnm_clock>;
 134                         };
 135
 136                         i2c0: i2c@11000{
 137                                 compatible = "marvell,mv78230-i2c";
 138                                 reg = <0x11000 0x20>;
 139                                 #address-cells = <1>;
 140                                 #size-cells = <0>;
 141
 142                                 clocks = <&cnm_clock>;
 143                                 clock-names = "core";
 144                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 145                                 clock-frequency=<100000>;
 146
 147                                 pinctrl-names = "default", "gpio";
 148                                 pinctrl-0 = <&i2c0_pins>;
 149                                 pinctrl-1 = <&i2c0_gpio>;
 150                                 scl-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 151                                 sda-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 152                                 status = "disabled";
 153                         };
 154
 155                         i2c1: i2c@11100{
 156                                 compatible = "marvell,mv78230-i2c";
 157                                 reg = <0x11100 0x20>;
 158                                 #address-cells = <1>;
 159                                 #size-cells = <0>;
 160
 161                                 clocks = <&cnm_clock>;
 162                                 clock-names = "core";
 163                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 164                                 clock-frequency=<100000>;
 165
 166                                 pinctrl-names = "default", "gpio";
 167                                 pinctrl-0 = <&i2c1_pins>;
 168                                 pinctrl-1 = <&i2c1_gpio>;
 169                                 scl-gpios = <&gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 170                                 sda-gpios = <&gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 171                                 status = "disabled";
 172                         };
 173
 174                         gpio0: gpio@18100 {
 175                                 compatible = "marvell,orion-gpio";
 176                                 reg = <0x18100 0x40>;
 177                                 ngpios = <32>;
 178                                 gpio-controller;
 179                                 #gpio-cells = <2>;
 180                                 gpio-ranges = <&pinctrl0 0 0 32>;
 181                                 marvell,pwm-offset = <0x1f0>;
 182                                 interrupt-controller;
 183                                 #interrupt-cells = <2>;
 184                                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
 185                                              <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 186                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 187                                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 188                         };
 189
 190                         gpio1: gpio@18140 {
 191                                 reg = <0x18140 0x40>;
 192                                 compatible = "marvell,orion-gpio";
 193                                 ngpios = <14>;
 194                                 gpio-controller;
 195                                 #gpio-cells = <2>;
 196                                 gpio-ranges = <&pinctrl0 0 32 14>;
 197                                 marvell,pwm-offset = <0x1f0>;
 198                                 interrupt-controller;
 199                                 #interrupt-cells = <2>;
 200                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
 201                                              <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 202                         };
 203                 };
 204
 205                 /*
 206                  * Dedicated section for devices behind 32bit controllers so we
 207                  * can configure specific DMA mapping for them
 208                  */
 209                 behind-32bit-controller@7f000000 {
 210                         compatible = "simple-bus";
 211                         #address-cells = <0x2>;
 212                         #size-cells = <0x2>;
 213                         ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
 214                         /* Host phy ram starts at 0x200M */
 215                         dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
 216                         dma-coherent;
 217
 218                         eth0: ethernet@20000 {
 219                                 compatible = "marvell,armada-ac5-neta";
 220                                 reg = <0x0 0x20000 0x0 0x4000>;
 221                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 222                                 clocks = <&cnm_clock>;
 223                                 phy-mode = "sgmii";
 224                                 status = "disabled";
 225                         };
 226
 227                         eth1: ethernet@24000 {
 228                                 compatible = "marvell,armada-ac5-neta";
 229                                 reg = <0x0 0x24000 0x0 0x4000>;
 230                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 231                                 clocks = <&cnm_clock>;
 232                                 phy-mode = "sgmii";
 233                                 status = "disabled";
 234                         };
 235
 236                         usb0: usb@80000 {
 237                                 compatible = "marvell,orion-ehci";
 238                                 reg = <0x0 0x80000 0x0 0x500>;
 239                                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 240                                 status = "disabled";
 241                         };
 242
 243                         usb1: usb@a0000 {
 244                                 compatible = "marvell,orion-ehci";
 245                                 reg = <0x0 0xa0000 0x0 0x500>;
 246                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 247                                 status = "disabled";
 248                         };
 249                 };
 250
 251                 pinctrl0: pinctrl@80020100 {
 252                         compatible = "marvell,ac5-pinctrl";
 253                         reg = <0 0x80020100 0 0x20>;
 254
 255                         i2c0_pins: i2c0-pins {
 256                                 marvell,pins = "mpp26", "mpp27";
 257                                 marvell,function = "i2c0";
 258                         };
 259
 260                         i2c0_gpio: i2c0-gpio-pins {
 261                                 marvell,pins = "mpp26", "mpp27";
 262                                 marvell,function = "gpio";
 263                         };
 264
 265                         i2c1_pins: i2c1-pins {
 266                                 marvell,pins = "mpp20", "mpp21";
 267                                 marvell,function = "i2c1";
 268                         };
 269
 270                         i2c1_gpio: i2c1-gpio-pins {
 271                                 marvell,pins = "mpp20", "mpp21";
 272                                 marvell,function = "i2c1";
 273                         };
 274                 };
 275
 276                 spi0: spi@805a0000 {
 277                         compatible = "marvell,armada-3700-spi";
 278                         reg = <0x0 0x805a0000 0x0 0x50>;
 279                         #address-cells = <0x1>;
 280                         #size-cells = <0x0>;
 281                         clocks = <&spi_clock>;
 282                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 283                         num-cs = <1>;
 284                         status = "disabled";
 285                 };
 286
 287                 spi1: spi@805a8000 {
 288                         compatible = "marvell,armada-3700-spi";
 289                         reg = <0x0 0x805a8000 0x0 0x50>;
 290                         #address-cells = <0x1>;
 291                         #size-cells = <0x0>;
 292                         clocks = <&spi_clock>;
 293                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 294                         num-cs = <1>;
 295                         status = "disabled";
 296                 };
 297
 298                 gic: interrupt-controller@80600000 {
 299                         compatible = "arm,gic-v3";
 300                         #interrupt-cells = <3>;
 301                         interrupt-controller;
 302                         reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
 303                               <0x0 0x80660000 0x0 0x40000>; /* GICR */
 304                         interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
 305                 };
 306         };
 307
 308         clocks {
 309                 cnm_clock: cnm-clock {
 310                         compatible = "fixed-clock";
 311                         #clock-cells = <0>;
 312                         clock-frequency = <328000000>;
 313                 };
 314
 315                 spi_clock: spi-clock {
 316                         compatible = "fixed-clock";
 317                         #clock-cells = <0>;
 318                         clock-frequency = <200000000>;
 319                 };
 320         };
 321 };