1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for lg1313 SoC
5 * Copyright (C) 2016, LG Electronics
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "lge,lg1313";
16 interrupt-parent = <&gic>;
24 compatible = "arm,cortex-a53";
26 next-level-cache = <&L2_0>;
30 compatible = "arm,cortex-a53";
32 enable-method = "psci";
33 next-level-cache = <&L2_0>;
37 compatible = "arm,cortex-a53";
39 enable-method = "psci";
40 next-level-cache = <&L2_0>;
44 compatible = "arm,cortex-a53";
46 enable-method = "psci";
47 next-level-cache = <&L2_0>;
57 compatible = "arm,psci-0.2", "arm,psci";
59 cpu_suspend = <0x84000001>;
60 cpu_off = <0x84000002>;
61 cpu_on = <0x84000003>;
64 gic: interrupt-controller@c0001000 {
65 #interrupt-cells = <3>;
66 compatible = "arm,gic-400";
68 reg = <0x0 0xc0001000 0x1000>,
69 <0x0 0xc0002000 0x2000>,
70 <0x0 0xc0004000 0x2000>,
71 <0x0 0xc0006000 0x2000>;
75 compatible = "arm,cortex-a53-pmu";
76 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
80 interrupt-affinity = <&cpu0>,
87 compatible = "arm,armv8-timer";
88 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |
90 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |
92 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |
94 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |
101 compatible = "fixed-clock";
102 clock-frequency = <198000000>;
103 clock-output-names = "BUSCLK";
107 #address-cells = <2>;
110 compatible = "simple-bus";
111 interrupt-parent = <&gic>;
114 eth0: ethernet@c3700000 {
115 compatible = "cdns,gem";
116 reg = <0x0 0xc3700000 0x1000>;
117 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&clk_bus>, <&clk_bus>;
119 clock-names = "hclk", "pclk";
121 /* Filled in by boot */
122 mac-address = [ 00 00 00 00 00 00 ];
127 #address-cells = <2>;
129 #interrupt-cells = <3>;
131 compatible = "simple-bus";
132 interrupt-parent = <&gic>;
135 timers: timer@fd100000 {
136 compatible = "arm,sp804", "arm,primecell";
137 reg = <0x0 0xfd100000 0x1000>;
138 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>;
140 clock-names = "timer0clk", "timer1clk", "apb_pclk";
142 wdog: watchdog@fd200000 {
143 compatible = "arm,sp805", "arm,primecell";
144 reg = <0x0 0xfd200000 0x1000>;
145 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&clk_bus>, <&clk_bus>;
147 clock-names = "wdog_clk", "apb_pclk";
149 uart0: serial@fe000000 {
150 compatible = "arm,pl011", "arm,primecell";
151 reg = <0x0 0xfe000000 0x1000>;
152 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
154 clock-names = "apb_pclk";
157 uart1: serial@fe100000 {
158 compatible = "arm,pl011", "arm,primecell";
159 reg = <0x0 0xfe100000 0x1000>;
160 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
162 clock-names = "apb_pclk";
165 uart2: serial@fe200000 {
166 compatible = "arm,pl011", "arm,primecell";
167 reg = <0x0 0xfe200000 0x1000>;
168 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
170 clock-names = "apb_pclk";
174 compatible = "arm,pl022", "arm,primecell";
175 reg = <0x0 0xfe800000 0x1000>;
176 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
178 clock-names = "apb_pclk";
181 compatible = "arm,pl022", "arm,primecell";
182 reg = <0x0 0xfe900000 0x1000>;
183 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
185 clock-names = "apb_pclk";
187 dmac0: dma-controller@c1128000 {
188 compatible = "arm,pl330", "arm,primecell";
189 reg = <0x0 0xc1128000 0x1000>;
190 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
192 clock-names = "apb_pclk";
195 gpio0: gpio@fd400000 {
197 compatible = "arm,pl061", "arm,primecell";
199 reg = <0x0 0xfd400000 0x1000>;
201 clock-names = "apb_pclk";
204 gpio1: gpio@fd410000 {
206 compatible = "arm,pl061", "arm,primecell";
208 reg = <0x0 0xfd410000 0x1000>;
210 clock-names = "apb_pclk";
213 gpio2: gpio@fd420000 {
215 compatible = "arm,pl061", "arm,primecell";
217 reg = <0x0 0xfd420000 0x1000>;
219 clock-names = "apb_pclk";
222 gpio3: gpio@fd430000 {
224 compatible = "arm,pl061", "arm,primecell";
226 reg = <0x0 0xfd430000 0x1000>;
228 clock-names = "apb_pclk";
230 gpio4: gpio@fd440000 {
232 compatible = "arm,pl061", "arm,primecell";
234 reg = <0x0 0xfd440000 0x1000>;
236 clock-names = "apb_pclk";
239 gpio5: gpio@fd450000 {
241 compatible = "arm,pl061", "arm,primecell";
243 reg = <0x0 0xfd450000 0x1000>;
245 clock-names = "apb_pclk";
248 gpio6: gpio@fd460000 {
250 compatible = "arm,pl061", "arm,primecell";
252 reg = <0x0 0xfd460000 0x1000>;
254 clock-names = "apb_pclk";
257 gpio7: gpio@fd470000 {
259 compatible = "arm,pl061", "arm,primecell";
261 reg = <0x0 0xfd470000 0x1000>;
263 clock-names = "apb_pclk";
266 gpio8: gpio@fd480000 {
268 compatible = "arm,pl061", "arm,primecell";
270 reg = <0x0 0xfd480000 0x1000>;
272 clock-names = "apb_pclk";
275 gpio9: gpio@fd490000 {
277 compatible = "arm,pl061", "arm,primecell";
279 reg = <0x0 0xfd490000 0x1000>;
281 clock-names = "apb_pclk";
284 gpio10: gpio@fd4a0000 {
286 compatible = "arm,pl061", "arm,primecell";
288 reg = <0x0 0xfd4a0000 0x1000>;
290 clock-names = "apb_pclk";
293 gpio11: gpio@fd4b0000 {
295 compatible = "arm,pl061", "arm,primecell";
297 reg = <0x0 0xfd4b0000 0x1000>;
299 clock-names = "apb_pclk";
301 gpio12: gpio@fd4c0000 {
303 compatible = "arm,pl061", "arm,primecell";
305 reg = <0x0 0xfd4c0000 0x1000>;
307 clock-names = "apb_pclk";
310 gpio13: gpio@fd4d0000 {
312 compatible = "arm,pl061", "arm,primecell";
314 reg = <0x0 0xfd4d0000 0x1000>;
316 clock-names = "apb_pclk";
319 gpio14: gpio@fd4e0000 {
321 compatible = "arm,pl061", "arm,primecell";
323 reg = <0x0 0xfd4e0000 0x1000>;
325 clock-names = "apb_pclk";
328 gpio15: gpio@fd4f0000 {
330 compatible = "arm,pl061", "arm,primecell";
332 reg = <0x0 0xfd4f0000 0x1000>;
334 clock-names = "apb_pclk";
337 gpio16: gpio@fd500000 {
339 compatible = "arm,pl061", "arm,primecell";
341 reg = <0x0 0xfd500000 0x1000>;
343 clock-names = "apb_pclk";
346 gpio17: gpio@fd510000 {
348 compatible = "arm,pl061", "arm,primecell";
350 reg = <0x0 0xfd510000 0x1000>;
352 clock-names = "apb_pclk";