1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021, Intel Corporation
5 #include "socfpga_agilex.dtsi"
8 model = "eASIC N5X SoCDK";
9 compatible = "intel,n5x-socdk", "intel,socfpga-agilex";
19 stdout-path = "serial0:115200n8";
23 device_type = "memory";
24 /* We expect the bootloader to fill in the reg */
25 reg = <0 0x80000000 0 0>;
29 sdram_edac: memory-controller@f87f8000 {
30 compatible = "snps,ddrc-3.80a";
31 reg = <0xf87f8000 0x400>;
32 interrupts = <0 175 4>;
39 compatible = "intel,easic-n5x-clkmgr";
47 max-frame-size = <9000>;
52 compatible = "snps,dwmac-mdio";
53 phy0: ethernet-phy@0 {
56 txd0-skew-ps = <0>; /* -420ps */
57 txd1-skew-ps = <0>; /* -420ps */
58 txd2-skew-ps = <0>; /* -420ps */
59 txd3-skew-ps = <0>; /* -420ps */
60 rxd0-skew-ps = <420>; /* 0ps */
61 rxd1-skew-ps = <420>; /* 0ps */
62 rxd2-skew-ps = <420>; /* 0ps */
63 rxd3-skew-ps = <420>; /* 0ps */
64 txen-skew-ps = <0>; /* -420ps */
65 txc-skew-ps = <900>; /* 0ps */
66 rxdv-skew-ps = <420>; /* 0ps */
67 rxc-skew-ps = <1680>; /* 780ps */
77 clk-phase-sd-hs = <0>, <135>;
81 clock-frequency = <25000000>;
89 compatible = "micron,mt25qu02g", "jedec,spi-nor";
91 spi-max-frequency = <100000000>;
94 cdns,page-size = <256>;
95 cdns,block-size = <16>;
96 cdns,read-delay = <2>;
103 compatible = "fixed-partitions";
104 #address-cells = <1>;
107 qspi_boot: partition@0 {
108 label = "Boot and fpga data";
109 reg = <0x0 0x03FE0000>;
112 qspi_rootfs: partition@3fe0000 {
113 label = "Root Filesystem - JFFS2";
114 reg = <0x03FE0000 0x0C020000>;
126 disable-over-current;