1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019, Intel Corporation
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
22 service_reserved: svcbuffer@0 {
23 compatible = "shared-dma-pool";
24 reg = <0x0 0x0 0x0 0x2000000>;
35 compatible = "arm,cortex-a53";
37 enable-method = "psci";
42 compatible = "arm,cortex-a53";
44 enable-method = "psci";
49 compatible = "arm,cortex-a53";
51 enable-method = "psci";
56 compatible = "arm,cortex-a53";
58 enable-method = "psci";
64 compatible = "arm,armv8-pmuv3";
65 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
69 interrupt-affinity = <&cpu0>,
73 interrupt-parent = <&intc>;
77 compatible = "arm,psci-0.2";
81 intc: interrupt-controller@fffc1000 {
82 compatible = "arm,gic-400", "arm,cortex-a15-gic";
83 #interrupt-cells = <3>;
85 reg = <0x0 0xfffc1000 0x0 0x1000>,
86 <0x0 0xfffc2000 0x0 0x2000>,
87 <0x0 0xfffc4000 0x0 0x2000>,
88 <0x0 0xfffc6000 0x0 0x2000>;
92 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
94 compatible = "fixed-clock";
97 cb_intosc_ls_clk: cb-intosc-ls-clk {
99 compatible = "fixed-clock";
102 f2s_free_clk: f2s-free-clk {
104 compatible = "fixed-clock";
109 compatible = "fixed-clock";
114 compatible = "fixed-clock";
115 clock-frequency = <200000000>;
120 compatible = "arm,armv8-timer";
121 interrupt-parent = <&intc>;
122 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
123 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
124 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
125 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
130 compatible = "usb-nop-xceiv";
134 #address-cells = <1>;
136 compatible = "simple-bus";
138 interrupt-parent = <&intc>;
139 ranges = <0 0 0 0xffffffff>;
142 #address-cells = <0x2>;
144 compatible = "fpga-region";
145 fpga-mgr = <&fpga_mgr>;
148 clkmgr: clock-controller@ffd10000 {
149 compatible = "intel,agilex-clkmgr";
150 reg = <0xffd10000 0x1000>;
154 gmac0: ethernet@ff800000 {
155 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
156 reg = <0xff800000 0x2000>;
157 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
158 interrupt-names = "macirq";
159 mac-address = [00 00 00 00 00 00];
160 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
161 reset-names = "stmmaceth", "ahb";
162 tx-fifo-depth = <16384>;
163 rx-fifo-depth = <16384>;
164 snps,multicast-filter-bins = <256>;
166 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
167 clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
168 clock-names = "stmmaceth", "ptp_ref";
172 gmac1: ethernet@ff802000 {
173 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
174 reg = <0xff802000 0x2000>;
175 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
176 interrupt-names = "macirq";
177 mac-address = [00 00 00 00 00 00];
178 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
179 reset-names = "stmmaceth", "ahb";
180 tx-fifo-depth = <16384>;
181 rx-fifo-depth = <16384>;
182 snps,multicast-filter-bins = <256>;
184 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
185 clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
186 clock-names = "stmmaceth", "ptp_ref";
190 gmac2: ethernet@ff804000 {
191 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
192 reg = <0xff804000 0x2000>;
193 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
194 interrupt-names = "macirq";
195 mac-address = [00 00 00 00 00 00];
196 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
197 reset-names = "stmmaceth", "ahb";
198 tx-fifo-depth = <16384>;
199 rx-fifo-depth = <16384>;
200 snps,multicast-filter-bins = <256>;
202 altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
203 clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
204 clock-names = "stmmaceth", "ptp_ref";
208 gpio0: gpio@ffc03200 {
209 #address-cells = <1>;
211 compatible = "snps,dw-apb-gpio";
212 reg = <0xffc03200 0x100>;
213 resets = <&rst GPIO0_RESET>;
216 porta: gpio-controller@0 {
217 compatible = "snps,dw-apb-gpio-port";
220 snps,nr-gpios = <24>;
222 interrupt-controller;
223 #interrupt-cells = <2>;
224 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
228 gpio1: gpio@ffc03300 {
229 #address-cells = <1>;
231 compatible = "snps,dw-apb-gpio";
232 reg = <0xffc03300 0x100>;
233 resets = <&rst GPIO1_RESET>;
236 portb: gpio-controller@0 {
237 compatible = "snps,dw-apb-gpio-port";
240 snps,nr-gpios = <24>;
242 interrupt-controller;
243 #interrupt-cells = <2>;
244 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
249 #address-cells = <1>;
251 compatible = "snps,designware-i2c";
252 reg = <0xffc02800 0x100>;
253 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
254 resets = <&rst I2C0_RESET>;
255 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
260 #address-cells = <1>;
262 compatible = "snps,designware-i2c";
263 reg = <0xffc02900 0x100>;
264 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
265 resets = <&rst I2C1_RESET>;
266 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
271 #address-cells = <1>;
273 compatible = "snps,designware-i2c";
274 reg = <0xffc02a00 0x100>;
275 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
276 resets = <&rst I2C2_RESET>;
277 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
282 #address-cells = <1>;
284 compatible = "snps,designware-i2c";
285 reg = <0xffc02b00 0x100>;
286 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
287 resets = <&rst I2C3_RESET>;
288 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
293 #address-cells = <1>;
295 compatible = "snps,designware-i2c";
296 reg = <0xffc02c00 0x100>;
297 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
298 resets = <&rst I2C4_RESET>;
299 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
304 #address-cells = <1>;
306 compatible = "altr,socfpga-dw-mshc";
307 reg = <0xff808000 0x1000>;
308 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
309 fifo-depth = <0x400>;
310 resets = <&rst SDMMC_RESET>;
311 reset-names = "reset";
312 clocks = <&clkmgr AGILEX_L4_MP_CLK>,
313 <&clkmgr AGILEX_SDMMC_CLK>;
314 clock-names = "biu", "ciu";
316 altr,sysmgr-syscon = <&sysmgr 0x28 4>;
320 nand: nand-controller@ffb90000 {
321 #address-cells = <1>;
323 compatible = "altr,socfpga-denali-nand";
324 reg = <0xffb90000 0x10000>,
326 reg-names = "nand_data", "denali_reg";
327 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clkmgr AGILEX_NAND_CLK>,
329 <&clkmgr AGILEX_NAND_X_CLK>,
330 <&clkmgr AGILEX_NAND_ECC_CLK>;
331 clock-names = "nand", "nand_x", "ecc";
332 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
336 ocram: sram@ffe00000 {
337 compatible = "mmio-sram";
338 reg = <0xffe00000 0x40000>;
339 #address-cells = <1>;
341 ranges = <0 0xffe00000 0x40000>;
344 pdma: dma-controller@ffda0000 {
345 compatible = "arm,pl330", "arm,primecell";
346 reg = <0xffda0000 0x1000>;
347 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
357 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
358 reset-names = "dma", "dma-ocp";
359 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
360 clock-names = "apb_pclk";
363 pinctrl0: pinctrl@ffd13000 {
364 compatible = "pinctrl-single";
365 #pinctrl-cells = <1>;
366 reg = <0xffd13000 0xa0>;
367 pinctrl-single,register-width = <32>;
368 pinctrl-single,function-mask = <0x0000000f>;
371 pinctrl1: pinconf@ffd13100 {
372 compatible = "pinctrl-single";
373 #pinctrl-cells = <1>;
374 reg = <0xffd13100 0x20>;
375 pinctrl-single,register-width = <32>;
378 rst: rstmgr@ffd11000 {
379 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
380 reg = <0xffd11000 0x100>;
384 smmu: iommu@fa000000 {
385 compatible = "arm,mmu-500", "arm,smmu-v2";
386 reg = <0xfa000000 0x40000>;
387 #global-interrupts = <2>;
389 interrupt-parent = <&intc>;
390 /* Global Secure Fault */
391 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
392 /* Global Non-secure Fault */
393 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
394 /* Non-secure Context Interrupts (32) */
395 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
427 stream-match-mask = <0x7ff0>;
428 clocks = <&clkmgr AGILEX_MPU_CCU_CLK>,
429 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>,
430 <&clkmgr AGILEX_L4_MAIN_CLK>;
435 compatible = "snps,dw-apb-ssi";
436 #address-cells = <1>;
438 reg = <0xffda4000 0x1000>;
439 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
440 resets = <&rst SPIM0_RESET>;
444 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
449 compatible = "snps,dw-apb-ssi";
450 #address-cells = <1>;
452 reg = <0xffda5000 0x1000>;
453 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
454 resets = <&rst SPIM1_RESET>;
458 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
462 sysmgr: sysmgr@ffd12000 {
463 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
464 reg = <0xffd12000 0x500>;
467 timer0: timer0@ffc03000 {
468 compatible = "snps,dw-apb-timer";
469 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
470 reg = <0xffc03000 0x100>;
471 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
472 clock-names = "timer";
475 timer1: timer1@ffc03100 {
476 compatible = "snps,dw-apb-timer";
477 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
478 reg = <0xffc03100 0x100>;
479 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
480 clock-names = "timer";
483 timer2: timer2@ffd00000 {
484 compatible = "snps,dw-apb-timer";
485 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
486 reg = <0xffd00000 0x100>;
487 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
488 clock-names = "timer";
491 timer3: timer3@ffd00100 {
492 compatible = "snps,dw-apb-timer";
493 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
494 reg = <0xffd00100 0x100>;
495 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
496 clock-names = "timer";
499 uart0: serial@ffc02000 {
500 compatible = "snps,dw-apb-uart";
501 reg = <0xffc02000 0x100>;
502 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
505 resets = <&rst UART0_RESET>;
507 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
510 uart1: serial@ffc02100 {
511 compatible = "snps,dw-apb-uart";
512 reg = <0xffc02100 0x100>;
513 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
516 resets = <&rst UART1_RESET>;
517 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
522 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
523 reg = <0xffb00000 0x40000>;
524 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
526 phy-names = "usb2-phy";
527 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
528 reset-names = "dwc2", "dwc2-ecc";
529 clocks = <&clkmgr AGILEX_USB_CLK>;
536 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
537 reg = <0xffb40000 0x40000>;
538 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
540 phy-names = "usb2-phy";
541 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
542 reset-names = "dwc2", "dwc2-ecc";
544 clocks = <&clkmgr AGILEX_USB_CLK>;
548 watchdog0: watchdog@ffd00200 {
549 compatible = "snps,dw-wdt";
550 reg = <0xffd00200 0x100>;
551 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
552 resets = <&rst WATCHDOG0_RESET>;
553 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
557 watchdog1: watchdog@ffd00300 {
558 compatible = "snps,dw-wdt";
559 reg = <0xffd00300 0x100>;
560 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
561 resets = <&rst WATCHDOG1_RESET>;
562 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
566 watchdog2: watchdog@ffd00400 {
567 compatible = "snps,dw-wdt";
568 reg = <0xffd00400 0x100>;
569 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
570 resets = <&rst WATCHDOG2_RESET>;
571 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
575 watchdog3: watchdog@ffd00500 {
576 compatible = "snps,dw-wdt";
577 reg = <0xffd00500 0x100>;
578 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
579 resets = <&rst WATCHDOG3_RESET>;
580 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
585 compatible = "altr,sdr-ctl", "syscon";
586 reg = <0xf8011100 0xc0>;
590 compatible = "altr,socfpga-s10-ecc-manager",
591 "altr,socfpga-a10-ecc-manager";
592 altr,sysmgr-syscon = <&sysmgr>;
593 #address-cells = <1>;
595 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
596 interrupt-controller;
597 #interrupt-cells = <2>;
601 compatible = "altr,sdram-edac-s10";
602 altr,sdr-syscon = <&sdr>;
603 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
607 compatible = "altr,socfpga-s10-ocram-ecc",
608 "altr,socfpga-a10-ocram-ecc";
609 reg = <0xff8cc000 0x100>;
610 altr,ecc-parent = <&ocram>;
611 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
615 compatible = "altr,socfpga-s10-usb-ecc",
616 "altr,socfpga-usb-ecc";
617 reg = <0xff8c4000 0x100>;
618 altr,ecc-parent = <&usb0>;
619 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
622 emac0-rx-ecc@ff8c0000 {
623 compatible = "altr,socfpga-s10-eth-mac-ecc",
624 "altr,socfpga-eth-mac-ecc";
625 reg = <0xff8c0000 0x100>;
626 altr,ecc-parent = <&gmac0>;
627 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
630 emac0-tx-ecc@ff8c0400 {
631 compatible = "altr,socfpga-s10-eth-mac-ecc",
632 "altr,socfpga-eth-mac-ecc";
633 reg = <0xff8c0400 0x100>;
634 altr,ecc-parent = <&gmac0>;
635 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
638 sdmmca-ecc@ff8c8c00 {
639 compatible = "altr,socfpga-s10-sdmmc-ecc",
640 "altr,socfpga-sdmmc-ecc";
641 reg = <0xff8c8c00 0x100>;
642 altr,ecc-parent = <&mmc>;
643 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
644 <15 IRQ_TYPE_LEVEL_HIGH>;
649 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
650 #address-cells = <1>;
652 reg = <0xff8d2000 0x100>,
653 <0xff900000 0x100000>;
654 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
655 cdns,fifo-depth = <128>;
656 cdns,fifo-width = <4>;
657 cdns,trigger-address = <0x00000000>;
658 clocks = <&qspi_clk>;
665 compatible = "intel,agilex-svc";
667 memory-region = <&service_reserved>;
670 compatible = "intel,agilex-soc-fpga-mgr";