1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019, Intel Corporation
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "intel,socfpga-agilex";
20 compatible = "arm,cortex-a53";
22 enable-method = "psci";
27 compatible = "arm,cortex-a53";
29 enable-method = "psci";
34 compatible = "arm,cortex-a53";
36 enable-method = "psci";
41 compatible = "arm,cortex-a53";
43 enable-method = "psci";
49 compatible = "arm,armv8-pmuv3";
50 interrupts = <0 170 4>,
54 interrupt-affinity = <&cpu0>,
58 interrupt-parent = <&intc>;
62 compatible = "arm,psci-0.2";
67 compatible = "arm,gic-400", "arm,cortex-a15-gic";
68 #interrupt-cells = <3>;
70 reg = <0x0 0xfffc1000 0x0 0x1000>,
71 <0x0 0xfffc2000 0x0 0x2000>,
72 <0x0 0xfffc4000 0x0 0x2000>,
73 <0x0 0xfffc6000 0x0 0x2000>;
79 compatible = "simple-bus";
81 interrupt-parent = <&intc>;
82 ranges = <0 0 0 0xffffffff>;
84 gmac0: ethernet@ff800000 {
85 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
86 reg = <0xff800000 0x2000>;
87 interrupts = <0 90 4>;
88 interrupt-names = "macirq";
89 mac-address = [00 00 00 00 00 00];
90 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
91 reset-names = "stmmaceth", "stmmaceth-ocp";
92 tx-fifo-depth = <16384>;
93 rx-fifo-depth = <16384>;
94 snps,multicast-filter-bins = <256>;
99 gmac1: ethernet@ff802000 {
100 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
101 reg = <0xff802000 0x2000>;
102 interrupts = <0 91 4>;
103 interrupt-names = "macirq";
104 mac-address = [00 00 00 00 00 00];
105 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
106 reset-names = "stmmaceth", "stmmaceth-ocp";
107 tx-fifo-depth = <16384>;
108 rx-fifo-depth = <16384>;
109 snps,multicast-filter-bins = <256>;
114 gmac2: ethernet@ff804000 {
115 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
116 reg = <0xff804000 0x2000>;
117 interrupts = <0 92 4>;
118 interrupt-names = "macirq";
119 mac-address = [00 00 00 00 00 00];
120 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
121 reset-names = "stmmaceth", "stmmaceth-ocp";
122 tx-fifo-depth = <16384>;
123 rx-fifo-depth = <16384>;
124 snps,multicast-filter-bins = <256>;
129 gpio0: gpio@ffc03200 {
130 #address-cells = <1>;
132 compatible = "snps,dw-apb-gpio";
133 reg = <0xffc03200 0x100>;
134 resets = <&rst GPIO0_RESET>;
137 porta: gpio-controller@0 {
138 compatible = "snps,dw-apb-gpio-port";
141 snps,nr-gpios = <24>;
143 interrupt-controller;
144 #interrupt-cells = <2>;
145 interrupts = <0 110 4>;
149 gpio1: gpio@ffc03300 {
150 #address-cells = <1>;
152 compatible = "snps,dw-apb-gpio";
153 reg = <0xffc03300 0x100>;
154 resets = <&rst GPIO1_RESET>;
157 portb: gpio-controller@0 {
158 compatible = "snps,dw-apb-gpio-port";
161 snps,nr-gpios = <24>;
163 interrupt-controller;
164 #interrupt-cells = <2>;
165 interrupts = <0 111 4>;
170 #address-cells = <1>;
172 compatible = "snps,designware-i2c";
173 reg = <0xffc02800 0x100>;
174 interrupts = <0 103 4>;
175 resets = <&rst I2C0_RESET>;
180 #address-cells = <1>;
182 compatible = "snps,designware-i2c";
183 reg = <0xffc02900 0x100>;
184 interrupts = <0 104 4>;
185 resets = <&rst I2C1_RESET>;
190 #address-cells = <1>;
192 compatible = "snps,designware-i2c";
193 reg = <0xffc02a00 0x100>;
194 interrupts = <0 105 4>;
195 resets = <&rst I2C2_RESET>;
200 #address-cells = <1>;
202 compatible = "snps,designware-i2c";
203 reg = <0xffc02b00 0x100>;
204 interrupts = <0 106 4>;
205 resets = <&rst I2C3_RESET>;
210 #address-cells = <1>;
212 compatible = "snps,designware-i2c";
213 reg = <0xffc02c00 0x100>;
214 interrupts = <0 107 4>;
215 resets = <&rst I2C4_RESET>;
219 mmc: dwmmc0@ff808000 {
220 #address-cells = <1>;
222 compatible = "altr,socfpga-dw-mshc";
223 reg = <0xff808000 0x1000>;
224 interrupts = <0 96 4>;
225 fifo-depth = <0x400>;
226 resets = <&rst SDMMC_RESET>;
227 reset-names = "reset";
232 ocram: sram@ffe00000 {
233 compatible = "mmio-sram";
234 reg = <0xffe00000 0x40000>;
237 pdma: pdma@ffda0000 {
238 compatible = "arm,pl330", "arm,primecell";
239 reg = <0xffda0000 0x1000>;
240 interrupts = <0 81 4>,
251 #dma-requests = <32>;
252 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
253 reset-names = "dma", "dma-ocp";
256 rst: rstmgr@ffd11000 {
258 compatible = "altr,stratix10-rst-mgr";
259 reg = <0xffd11000 0x100>;
262 smmu: iommu@fa000000 {
263 compatible = "arm,mmu-500", "arm,smmu-v2";
264 reg = <0xfa000000 0x40000>;
265 #global-interrupts = <2>;
267 interrupt-parent = <&intc>;
268 interrupts = <0 128 4>, /* Global Secure Fault */
269 <0 129 4>, /* Global Non-secure Fault */
270 /* Non-secure Context Interrupts (32) */
271 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
272 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
273 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
274 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
275 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
276 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
277 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
278 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
279 stream-match-mask = <0x7ff0>;
284 compatible = "snps,dw-apb-ssi";
285 #address-cells = <1>;
287 reg = <0xffda4000 0x1000>;
288 interrupts = <0 99 4>;
289 resets = <&rst SPIM0_RESET>;
296 compatible = "snps,dw-apb-ssi";
297 #address-cells = <1>;
299 reg = <0xffda5000 0x1000>;
300 interrupts = <0 100 4>;
301 resets = <&rst SPIM1_RESET>;
307 sysmgr: sysmgr@ffd12000 {
308 compatible = "altr,sys-mgr", "syscon";
309 reg = <0xffd12000 0x500>;
314 compatible = "arm,armv8-timer";
315 interrupts = <1 13 0xf08>,
321 timer0: timer0@ffc03000 {
322 compatible = "snps,dw-apb-timer";
323 interrupts = <0 113 4>;
324 reg = <0xffc03000 0x100>;
327 timer1: timer1@ffc03100 {
328 compatible = "snps,dw-apb-timer";
329 interrupts = <0 114 4>;
330 reg = <0xffc03100 0x100>;
333 timer2: timer2@ffd00000 {
334 compatible = "snps,dw-apb-timer";
335 interrupts = <0 115 4>;
336 reg = <0xffd00000 0x100>;
339 timer3: timer3@ffd00100 {
340 compatible = "snps,dw-apb-timer";
341 interrupts = <0 116 4>;
342 reg = <0xffd00100 0x100>;
345 uart0: serial0@ffc02000 {
346 compatible = "snps,dw-apb-uart";
347 reg = <0xffc02000 0x100>;
348 interrupts = <0 108 4>;
351 resets = <&rst UART0_RESET>;
355 uart1: serial1@ffc02100 {
356 compatible = "snps,dw-apb-uart";
357 reg = <0xffc02100 0x100>;
358 interrupts = <0 109 4>;
361 resets = <&rst UART1_RESET>;
367 compatible = "usb-nop-xceiv";
372 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
373 reg = <0xffb00000 0x40000>;
374 interrupts = <0 93 4>;
376 phy-names = "usb2-phy";
377 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
378 reset-names = "dwc2", "dwc2-ecc";
384 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
385 reg = <0xffb40000 0x40000>;
386 interrupts = <0 94 4>;
388 phy-names = "usb2-phy";
389 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
390 reset-names = "dwc2", "dwc2-ecc";
395 watchdog0: watchdog@ffd00200 {
396 compatible = "snps,dw-wdt";
397 reg = <0xffd00200 0x100>;
398 interrupts = <0 117 4>;
399 resets = <&rst WATCHDOG0_RESET>;
403 watchdog1: watchdog@ffd00300 {
404 compatible = "snps,dw-wdt";
405 reg = <0xffd00300 0x100>;
406 interrupts = <0 118 4>;
407 resets = <&rst WATCHDOG1_RESET>;
411 watchdog2: watchdog@ffd00400 {
412 compatible = "snps,dw-wdt";
413 reg = <0xffd00400 0x100>;
414 interrupts = <0 125 4>;
415 resets = <&rst WATCHDOG2_RESET>;
419 watchdog3: watchdog@ffd00500 {
420 compatible = "snps,dw-wdt";
421 reg = <0xffd00500 0x100>;
422 interrupts = <0 126 4>;
423 resets = <&rst WATCHDOG3_RESET>;
428 compatible = "altr,sdr-ctl", "syscon";
429 reg = <0xf8011100 0xc0>;
433 compatible = "cdns,qspi-nor";
434 #address-cells = <1>;
436 reg = <0xff8d2000 0x100>,
437 <0xff900000 0x100000>;
438 interrupts = <0 3 4>;
439 cdns,fifo-depth = <128>;
440 cdns,fifo-width = <4>;
441 cdns,trigger-address = <0x00000000>;