1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 * Copyright (C) 2020, Intel Corporation.
5 * Device tree describing Keem Bay SoC.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
30 enable-method = "psci";
34 compatible = "arm,cortex-a53";
37 enable-method = "psci";
41 compatible = "arm,cortex-a53";
44 enable-method = "psci";
49 compatible = "arm,psci-0.2";
53 gic: interrupt-controller@20500000 {
54 compatible = "arm,gic-v3";
56 #interrupt-cells = <3>;
57 reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */
58 <0x0 0x20580000 0x0 0x80000>; /* GICR */
59 /* VGIC maintenance interrupt */
60 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
64 compatible = "arm,armv8-timer";
65 /* Secure, non-secure, virtual, and hypervisor */
66 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
73 compatible = "arm,armv8-pmuv3";
74 interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>;
78 compatible = "simple-bus";
83 uart0: serial@20150000 {
84 compatible = "snps,dw-apb-uart";
85 reg = <0x0 0x20150000 0x0 0x100>;
86 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
87 clock-frequency = <24000000>;
93 uart1: serial@20160000 {
94 compatible = "snps,dw-apb-uart";
95 reg = <0x0 0x20160000 0x0 0x100>;
96 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
97 clock-frequency = <24000000>;
103 uart2: serial@20170000 {
104 compatible = "snps,dw-apb-uart";
105 reg = <0x0 0x20170000 0x0 0x100>;
106 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
107 clock-frequency = <24000000>;
113 uart3: serial@20180000 {
114 compatible = "snps,dw-apb-uart";
115 reg = <0x0 0x20180000 0x0 0x100>;
116 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
117 clock-frequency = <24000000>;