arch/arm64/boot/dts/hisilicon/hip06.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /**
   3  * dts file for Hisilicon D03 Development Board
   4  *
   5  * Copyright (C) 2016 HiSilicon Ltd.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 / {
  11         compatible = "hisilicon,hip06-d03";
  12         interrupt-parent = <&gic>;
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         psci {
  17                 compatible = "arm,psci-0.2";
  18                 method = "smc";
  19         };
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu-map {
  26                         cluster0 {
  27                                 core0 {
  28                                         cpu = <&cpu0>;
  29                                 };
  30                                 core1 {
  31                                         cpu = <&cpu1>;
  32                                 };
  33                                 core2 {
  34                                         cpu = <&cpu2>;
  35                                 };
  36                                 core3 {
  37                                         cpu = <&cpu3>;
  38                                 };
  39                         };
  40                         cluster1 {
  41                                 core0 {
  42                                         cpu = <&cpu4>;
  43                                 };
  44                                 core1 {
  45                                         cpu = <&cpu5>;
  46                                 };
  47                                 core2 {
  48                                         cpu = <&cpu6>;
  49                                 };
  50                                 core3 {
  51                                         cpu = <&cpu7>;
  52                                 };
  53                         };
  54                         cluster2 {
  55                                 core0 {
  56                                         cpu = <&cpu8>;
  57                                 };
  58                                 core1 {
  59                                         cpu = <&cpu9>;
  60                                 };
  61                                 core2 {
  62                                         cpu = <&cpu10>;
  63                                 };
  64                                 core3 {
  65                                         cpu = <&cpu11>;
  66                                 };
  67                         };
  68                         cluster3 {
  69                                 core0 {
  70                                         cpu = <&cpu12>;
  71                                 };
  72                                 core1 {
  73                                         cpu = <&cpu13>;
  74                                 };
  75                                 core2 {
  76                                         cpu = <&cpu14>;
  77                                 };
  78                                 core3 {
  79                                         cpu = <&cpu15>;
  80                                 };
  81                         };
  82                 };
  83
  84                 cpu0: cpu@10000 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a57";
  87                         reg = <0x10000>;
  88                         enable-method = "psci";
  89                         next-level-cache = <&cluster0_l2>;
  90                 };
  91
  92                 cpu1: cpu@10001 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a57";
  95                         reg = <0x10001>;
  96                         enable-method = "psci";
  97                         next-level-cache = <&cluster0_l2>;
  98                 };
  99
 100                 cpu2: cpu@10002 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a57";
 103                         reg = <0x10002>;
 104                         enable-method = "psci";
 105                         next-level-cache = <&cluster0_l2>;
 106                 };
 107
 108                 cpu3: cpu@10003 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a57";
 111                         reg = <0x10003>;
 112                         enable-method = "psci";
 113                         next-level-cache = <&cluster0_l2>;
 114                 };
 115
 116                 cpu4: cpu@10100 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a57";
 119                         reg = <0x10100>;
 120                         enable-method = "psci";
 121                         next-level-cache = <&cluster1_l2>;
 122                 };
 123
 124                 cpu5: cpu@10101 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a57";
 127                         reg = <0x10101>;
 128                         enable-method = "psci";
 129                         next-level-cache = <&cluster1_l2>;
 130                 };
 131
 132                 cpu6: cpu@10102 {
 133                         device_type = "cpu";
 134                         compatible = "arm,cortex-a57";
 135                         reg = <0x10102>;
 136                         enable-method = "psci";
 137                         next-level-cache = <&cluster1_l2>;
 138                 };
 139
 140                 cpu7: cpu@10103 {
 141                         device_type = "cpu";
 142                         compatible = "arm,cortex-a57";
 143                         reg = <0x10103>;
 144                         enable-method = "psci";
 145                         next-level-cache = <&cluster1_l2>;
 146                 };
 147
 148                 cpu8: cpu@10200 {
 149                         device_type = "cpu";
 150                         compatible = "arm,cortex-a57";
 151                         reg = <0x10200>;
 152                         enable-method = "psci";
 153                         next-level-cache = <&cluster2_l2>;
 154                 };
 155
 156                 cpu9: cpu@10201 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a57";
 159                         reg = <0x10201>;
 160                         enable-method = "psci";
 161                         next-level-cache = <&cluster2_l2>;
 162                 };
 163
 164                 cpu10: cpu@10202 {
 165                         device_type = "cpu";
 166                         compatible = "arm,cortex-a57";
 167                         reg = <0x10202>;
 168                         enable-method = "psci";
 169                         next-level-cache = <&cluster2_l2>;
 170                 };
 171
 172                 cpu11: cpu@10203 {
 173                         device_type = "cpu";
 174                         compatible = "arm,cortex-a57";
 175                         reg = <0x10203>;
 176                         enable-method = "psci";
 177                         next-level-cache = <&cluster2_l2>;
 178                 };
 179
 180                 cpu12: cpu@10300 {
 181                         device_type = "cpu";
 182                         compatible = "arm,cortex-a57";
 183                         reg = <0x10300>;
 184                         enable-method = "psci";
 185                         next-level-cache = <&cluster3_l2>;
 186                 };
 187
 188                 cpu13: cpu@10301 {
 189                         device_type = "cpu";
 190                         compatible = "arm,cortex-a57";
 191                         reg = <0x10301>;
 192                         enable-method = "psci";
 193                         next-level-cache = <&cluster3_l2>;
 194                 };
 195
 196                 cpu14: cpu@10302 {
 197                         device_type = "cpu";
 198                         compatible = "arm,cortex-a57";
 199                         reg = <0x10302>;
 200                         enable-method = "psci";
 201                         next-level-cache = <&cluster3_l2>;
 202                 };
 203
 204                 cpu15: cpu@10303 {
 205                         device_type = "cpu";
 206                         compatible = "arm,cortex-a57";
 207                         reg = <0x10303>;
 208                         enable-method = "psci";
 209                         next-level-cache = <&cluster3_l2>;
 210                 };
 211
 212                 cluster0_l2: l2-cache0 {
 213                         compatible = "cache";
 214                         cache-level = <2>;
 215                         cache-unified;
 216                 };
 217
 218                 cluster1_l2: l2-cache1 {
 219                         compatible = "cache";
 220                         cache-level = <2>;
 221                         cache-unified;
 222                 };
 223
 224                 cluster2_l2: l2-cache2 {
 225                         compatible = "cache";
 226                         cache-level = <2>;
 227                         cache-unified;
 228                 };
 229
 230                 cluster3_l2: l2-cache3 {
 231                         compatible = "cache";
 232                         cache-level = <2>;
 233                         cache-unified;
 234                 };
 235         };
 236
 237         gic: interrupt-controller@4d000000 {
 238                 compatible = "arm,gic-v3";
 239                 #interrupt-cells = <3>;
 240                 #address-cells = <2>;
 241                 #size-cells = <2>;
 242                 ranges;
 243                 interrupt-controller;
 244                 #redistributor-regions = <1>;
 245                 redistributor-stride = <0x0 0x30000>;
 246                 reg = <0x0 0x4d000000 0 0x10000>,       /* GICD */
 247                       <0x0 0x4d100000 0 0x300000>,      /* GICR */
 248                       <0x0 0xfe000000 0 0x10000>,       /* GICC */
 249                       <0x0 0xfe010000 0 0x10000>,       /* GICH */
 250                       <0x0 0xfe020000 0 0x10000>;       /* GICV */
 251                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 252
 253                 its_dsa: msi-controller@c6000000 {
 254                         compatible = "arm,gic-v3-its";
 255                         msi-controller;
 256                         #msi-cells = <1>;
 257                         reg = <0x0 0xc6000000 0x0 0x40000>;
 258                 };
 259         };
 260
 261         timer {
 262                 compatible = "arm,armv8-timer";
 263                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 264                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 265                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 266                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 267         };
 268
 269         pmu {
 270                 compatible = "arm,cortex-a57-pmu";
 271                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 272         };
 273
 274         mbigen_pcie@a0080000 {
 275                 compatible = "hisilicon,mbigen-v2";
 276                 reg = <0x0 0xa0080000 0x0 0x10000>;
 277
 278                 mbigen_usb: intc_usb {
 279                         msi-parent = <&its_dsa 0x40080>;
 280                         interrupt-controller;
 281                         #interrupt-cells = <2>;
 282                         num-pins = <2>;
 283                 };
 284
 285                 mbigen_sas1: intc_sas1 {
 286                         msi-parent = <&its_dsa 0x40000>;
 287                         interrupt-controller;
 288                         #interrupt-cells = <2>;
 289                         num-pins = <128>;
 290                 };
 291
 292                 mbigen_sas2: intc_sas2 {
 293                         msi-parent = <&its_dsa 0x40040>;
 294                         interrupt-controller;
 295                         #interrupt-cells = <2>;
 296                         num-pins = <128>;
 297                 };
 298
 299                 mbigen_pcie0: intc_pcie0 {
 300                         msi-parent = <&its_dsa 0x40085>;
 301                         interrupt-controller;
 302                         #interrupt-cells = <2>;
 303                         num-pins = <10>;
 304                 };
 305         };
 306
 307         mbigen_dsa@c0080000 {
 308                 compatible = "hisilicon,mbigen-v2";
 309                 reg = <0x0 0xc0080000 0x0 0x10000>;
 310
 311                 mbigen_dsaf0: intc_dsaf0 {
 312                         msi-parent = <&its_dsa 0x40800>;
 313                         interrupt-controller;
 314                         #interrupt-cells = <2>;
 315                         num-pins = <409>;
 316                 };
 317
 318                 mbigen_sas0: intc-sas0 {
 319                         msi-parent = <&its_dsa 0x40900>;
 320                         interrupt-controller;
 321                         #interrupt-cells = <2>;
 322                         num-pins = <128>;
 323                 };
 324         };
 325
 326         /**
 327          *  HiSilicon erratum 161010801: This describes the limitation
 328          *  of HiSilicon platforms hip06/hip07 to support the SMMUv3
 329          *  mappings for PCIe MSI transactions.
 330          *  PCIe controller on these platforms has to differentiate the
 331          *  MSI payload against other DMA payload and has to modify the
 332          *  MSI payload. This makes it difficult for these platforms to
 333          *  have a SMMU translation for MSI. In order to workaround this,
 334          *  ARM SMMUv3 driver requires a quirk to treat the MSI regions
 335          *  separately. Such a quirk is currently missing for DT based
 336          *  systems. Hence please make sure that the smmu pcie node on
 337          *  hip06 is disabled as this will break the PCIe functionality
 338          *  when iommu-map entry is used along with the PCIe node.
 339          *  Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
 340          */
 341         smmu0: iommu@a0040000 {
 342                 compatible = "arm,smmu-v3";
 343                 reg = <0x0 0xa0040000 0x0 0x20000>;
 344                 #iommu-cells = <1>;
 345                 dma-coherent;
 346                 hisilicon,broken-prefetch-cmd;
 347                 status = "disabled";
 348         };
 349
 350         soc {
 351                 compatible = "simple-bus";
 352                 #address-cells = <2>;
 353                 #size-cells = <2>;
 354                 ranges;
 355
 356                 isa@a01b0000 {
 357                         compatible = "hisilicon,hip06-lpc";
 358                         #size-cells = <1>;
 359                         #address-cells = <2>;
 360                         reg = <0x0 0xa01b0000 0x0 0x1000>;
 361
 362                         ipmi0: bt@e4 {
 363                                 compatible = "ipmi-bt";
 364                                 device_type = "ipmi";
 365                                 reg = <0x01 0xe4 0x04>;
 366                                 status = "disabled";
 367                         };
 368
 369                         uart0: serial@2f8 {
 370                                 compatible = "ns16550a";
 371                                 clock-frequency = <1843200>;
 372                                 reg = <0x01 0x2f8 0x08>;
 373                                 status = "disabled";
 374                         };
 375                 };
 376
 377                 refclk: refclk {
 378                         compatible = "fixed-clock";
 379                         clock-frequency = <50000000>;
 380                         #clock-cells = <0>;
 381                 };
 382
 383                 usb_ohci: usb@a7030000 {
 384                         compatible = "generic-ohci";
 385                         reg = <0x0 0xa7030000 0x0 0x10000>;
 386                         interrupt-parent = <&mbigen_usb>;
 387                         interrupts = <640 4>;
 388                         dma-coherent;
 389                         status = "disabled";
 390                 };
 391
 392                 usb_ehci: usb@a7020000 {
 393                         compatible = "generic-ehci";
 394                         reg = <0x0 0xa7020000 0x0 0x10000>;
 395                         interrupt-parent = <&mbigen_usb>;
 396                         interrupts = <641 4>;
 397                         dma-coherent;
 398                         status = "disabled";
 399                 };
 400
 401                 peri_c_subctrl: sub_ctrl_c@60000000 {
 402                         compatible = "hisilicon,peri-subctrl","syscon";
 403                         reg = <0 0x60000000 0x0 0x10000>;
 404                 };
 405
 406                 dsa_subctrl: dsa_subctrl@c0000000 {
 407                         compatible = "hisilicon,dsa-subctrl", "syscon";
 408                         reg = <0x0 0xc0000000 0x0 0x10000>;
 409                 };
 410
 411                 pcie_subctl: pcie_subctl@a0000000 {
 412                         compatible = "hisilicon,pcie-sas-subctrl", "syscon";
 413                         reg = <0x0 0xa0000000 0x0 0x10000>;
 414                 };
 415
 416                 serdes_ctrl: sds_ctrl@c2200000 {
 417                         compatible = "syscon";
 418                         reg = <0 0xc2200000 0x0 0x80000>;
 419                 };
 420
 421                 mdio@603c0000 {
 422                         compatible = "hisilicon,hns-mdio";
 423                         reg = <0x0 0x603c0000 0x0 0x1000>;
 424                         subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>;
 425                         #address-cells = <1>;
 426                         #size-cells = <0>;
 427
 428                         phy0: ethernet-phy@0 {
 429                                 compatible = "ethernet-phy-ieee802.3-c22";
 430                                 reg = <0>;
 431                         };
 432
 433                         phy1: ethernet-phy@1 {
 434                                 compatible = "ethernet-phy-ieee802.3-c22";
 435                                 reg = <1>;
 436                         };
 437                 };
 438
 439                 dsaf0: dsa@c7000000 {
 440                         #address-cells = <1>;
 441                         #size-cells = <0>;
 442                         compatible = "hisilicon,hns-dsaf-v2";
 443                         mode = "6port-16rss";
 444                         reg = <0x0 0xc5000000 0x0 0x890000>,
 445                               <0x0 0xc7000000 0x0 0x600000>;
 446                         reg-names = "ppe-base", "dsaf-base";
 447                         interrupt-parent = <&mbigen_dsaf0>;
 448                         subctrl-syscon = <&dsa_subctrl>;
 449                         reset-field-offset = <0>;
 450                         interrupts =
 451                         <576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
 452                         <581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
 453                         <586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
 454                         <591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
 455                         <596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
 456                         <960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
 457                         <965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
 458                         <970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
 459                         <975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
 460                         <980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
 461                         <985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
 462                         <990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
 463                         <995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
 464                         <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
 465                         <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
 466                         <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
 467                         <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
 468                         <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
 469                         <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
 470                         <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
 471                         <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
 472                         <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
 473                         <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
 474                         <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
 475                         <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
 476                         <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
 477                         <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
 478                         <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
 479                         <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
 480                         <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
 481                         <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
 482                         <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
 483                         <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
 484                         <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>,
 485                         <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>,
 486                         <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>,
 487                         <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>,
 488                         <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>,
 489                         <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>,
 490                         <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>,
 491                         <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>,
 492                         <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>,
 493                         <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>,
 494                         <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>,
 495                         <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>,
 496                         <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>,
 497                         <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>,
 498                         <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>,
 499                         <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>,
 500                         <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>,
 501                         <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>,
 502                         <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>,
 503                         <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>,
 504                         <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>,
 505                         <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>,
 506                         <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>,
 507                         <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>,
 508                         <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>,
 509                         <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>,
 510                         <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>,
 511                         <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>,
 512                         <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>,
 513                         <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>,
 514                         <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>,
 515                         <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>,
 516                         <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>,
 517                         <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>,
 518                         <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>,
 519                         <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>,
 520                         <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>,
 521                         <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>,
 522                         <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>,
 523                         <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>,
 524                         <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>,
 525                         <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>,
 526                         <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>,
 527                         <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>,
 528                         <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>,
 529                         <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>,
 530                         <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>,
 531                         <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>,
 532                         <1340 1>, <1341 1>, <1342 1>, <1343 1>;
 533
 534                         desc-num = <0x400>;
 535                         buf-size = <0x1000>;
 536                         dma-coherent;
 537
 538                         port@0 {
 539                                 reg = <0>;
 540                                 serdes-syscon = <&serdes_ctrl>;
 541                                 port-rst-offset = <0>;
 542                                 port-mode-offset = <0>;
 543                                 media-type = "fiber";
 544                         };
 545
 546                         port@1 {
 547                                 reg = <1>;
 548                                 serdes-syscon = <&serdes_ctrl>;
 549                                 port-rst-offset = <1>;
 550                                 port-mode-offset = <1>;
 551                                 media-type = "fiber";
 552                         };
 553
 554                         port@4 {
 555                                 reg = <4>;
 556                                 phy-handle = <&phy0>;
 557                                 serdes-syscon = <&serdes_ctrl>;
 558                                 port-rst-offset = <4>;
 559                                 port-mode-offset = <2>;
 560                                 media-type = "copper";
 561                         };
 562
 563                         port@5 {
 564                                 reg = <5>;
 565                                 phy-handle = <&phy1>;
 566                                 serdes-syscon = <&serdes_ctrl>;
 567                                 port-rst-offset = <5>;
 568                                 port-mode-offset = <3>;
 569                                 media-type = "copper";
 570                         };
 571                 };
 572
 573                 eth0: ethernet-4 {
 574                         compatible = "hisilicon,hns-nic-v2";
 575                         ae-handle = <&dsaf0>;
 576                         port-idx-in-ae = <4>;
 577                         local-mac-address = [00 00 00 00 00 00];
 578                         status = "disabled";
 579                         dma-coherent;
 580                 };
 581
 582                 eth1: ethernet-5 {
 583                         compatible = "hisilicon,hns-nic-v2";
 584                         ae-handle = <&dsaf0>;
 585                         port-idx-in-ae = <5>;
 586                         local-mac-address = [00 00 00 00 00 00];
 587                         status = "disabled";
 588                         dma-coherent;
 589                 };
 590
 591                 eth2: ethernet-0 {
 592                         compatible = "hisilicon,hns-nic-v2";
 593                         ae-handle = <&dsaf0>;
 594                         port-idx-in-ae = <0>;
 595                         local-mac-address = [00 00 00 00 00 00];
 596                         status = "disabled";
 597                         dma-coherent;
 598                 };
 599
 600                 eth3: ethernet-1 {
 601                         compatible = "hisilicon,hns-nic-v2";
 602                         ae-handle = <&dsaf0>;
 603                         port-idx-in-ae = <1>;
 604                         local-mac-address = [00 00 00 00 00 00];
 605                         status = "disabled";
 606                         dma-coherent;
 607                 };
 608
 609                 sas0: sas@c3000000 {
 610                         compatible = "hisilicon,hip06-sas-v2";
 611                         reg = <0 0xc3000000 0 0x10000>;
 612                         sas-addr = [50 01 88 20 16 00 00 00];
 613                         hisilicon,sas-syscon = <&dsa_subctrl>;
 614                         ctrl-reset-reg = <0xa60>;
 615                         ctrl-reset-sts-reg = <0x5a30>;
 616                         ctrl-clock-ena-reg = <0x338>;
 617                         clocks = <&refclk 0>;
 618                         queue-count = <16>;
 619                         phy-count = <8>;
 620                         dma-coherent;
 621                         interrupt-parent = <&mbigen_sas0>;
 622                         interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
 623                                      <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
 624                                      <75 4>,<76 4>,<77 4>,<78 4>,<79 4>,
 625                                      <80 4>,<81 4>,<82 4>,<83 4>,<84 4>,
 626                                      <85 4>,<86 4>,<87 4>,<88 4>,<89 4>,
 627                                      <90 4>,<91 4>,<92 4>,<93 4>,<94 4>,
 628                                      <95 4>,<96 4>,<97 4>,<98 4>,<99 4>,
 629                                      <100 4>,<101 4>,<102 4>,<103 4>,<104 4>,
 630                                      <105 4>,<106 4>,<107 4>,<108 4>,<109 4>,
 631                                      <110 4>,<111 4>,<112 4>,<113 4>,<114 4>,
 632                                      <115 4>,<116 4>,<117 4>,<118 4>,<119 4>,
 633                                      <120 4>,<121 4>,<122 4>,<123 4>,<124 4>,
 634                                      <125 4>,<126 4>,<127 4>,<128 4>,<129 4>,
 635                                      <130 4>,<131 4>,<132 4>,<133 4>,<134 4>,
 636                                      <135 4>,<136 4>,<137 4>,<138 4>,<139 4>,
 637                                      <140 4>,<141 4>,<142 4>,<143 4>,<144 4>,
 638                                      <145 4>,<146 4>,<147 4>,<148 4>,<149 4>,
 639                                      <150 4>,<151 4>,<152 4>,<153 4>,<154 4>,
 640                                      <155 4>,<156 4>,<157 4>,<158 4>,<159 4>,
 641                                      <160 4>,<601 1>,<602 1>,<603 1>,<604 1>,
 642                                      <605 1>,<606 1>,<607 1>,<608 1>,<609 1>,
 643                                      <610 1>,<611 1>,<612 1>,<613 1>,<614 1>,
 644                                      <615 1>,<616 1>,<617 1>,<618 1>,<619 1>,
 645                                      <620 1>,<621 1>,<622 1>,<623 1>,<624 1>,
 646                                      <625 1>,<626 1>,<627 1>,<628 1>,<629 1>,
 647                                      <630 1>,<631 1>,<632 1>;
 648                         status = "disabled";
 649                 };
 650
 651                 sas1: sas@a2000000 {
 652                         compatible = "hisilicon,hip06-sas-v2";
 653                         reg = <0 0xa2000000 0 0x10000>;
 654                         sas-addr = [50 01 88 20 16 00 00 00];
 655                         hisilicon,sas-syscon = <&pcie_subctl>;
 656                         hip06-sas-v2-quirk-amt;
 657                         ctrl-reset-reg = <0xa18>;
 658                         ctrl-reset-sts-reg = <0x5a0c>;
 659                         ctrl-clock-ena-reg = <0x318>;
 660                         clocks = <&refclk 0>;
 661                         queue-count = <16>;
 662                         phy-count = <8>;
 663                         dma-coherent;
 664                         interrupt-parent = <&mbigen_sas1>;
 665                         interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
 666                                      <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
 667                                      <74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
 668                                      <79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
 669                                      <84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
 670                                      <89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
 671                                      <94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
 672                                      <99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
 673                                      <104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
 674                                      <109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
 675                                      <114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
 676                                      <119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
 677                                      <124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
 678                                      <129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
 679                                      <134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
 680                                      <139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
 681                                      <144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
 682                                      <149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
 683                                      <154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
 684                                      <159 4>,<576 1>,<577 1>,<578 1>,<579 1>,
 685                                      <580 1>,<581 1>,<582 1>,<583 1>,<584 1>,
 686                                      <585 1>,<586 1>,<587 1>,<588 1>,<589 1>,
 687                                      <590 1>,<591 1>,<592 1>,<593 1>,<594 1>,
 688                                      <595 1>,<596 1>,<597 1>,<598 1>,<599 1>,
 689                                      <600 1>,<601 1>,<602 1>,<603 1>,<604 1>,
 690                                      <605 1>,<606 1>,<607 1>;
 691                         status = "disabled";
 692                 };
 693
 694                 sas2: sas@a3000000 {
 695                         compatible = "hisilicon,hip06-sas-v2";
 696                         reg = <0 0xa3000000 0 0x10000>;
 697                         sas-addr = [50 01 88 20 16 00 00 00];
 698                         hisilicon,sas-syscon = <&pcie_subctl>;
 699                         ctrl-reset-reg = <0xae0>;
 700                         ctrl-reset-sts-reg = <0x5a70>;
 701                         ctrl-clock-ena-reg = <0x3a8>;
 702                         clocks = <&refclk 0>;
 703                         queue-count = <16>;
 704                         phy-count = <9>;
 705                         dma-coherent;
 706                         interrupt-parent = <&mbigen_sas2>;
 707                         interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>,
 708                                      <197 4>,<198 4>,<199 4>,<200 4>,<201 4>,
 709                                      <202 4>,<203 4>,<204 4>,<205 4>,<206 4>,
 710                                      <207 4>,<208 4>,<209 4>,<210 4>,<211 4>,
 711                                      <212 4>,<213 4>,<214 4>,<215 4>,<216 4>,
 712                                      <217 4>,<218 4>,<219 4>,<220 4>,<221 4>,
 713                                      <222 4>,<223 4>,<224 4>,<225 4>,<226 4>,
 714                                      <227 4>,<228 4>,<229 4>,<230 4>,<231 4>,
 715                                      <232 4>,<233 4>,<234 4>,<235 4>,<236 4>,
 716                                      <237 4>,<238 4>,<239 4>,<240 4>,<241 4>,
 717                                      <242 4>,<243 4>,<244 4>,<245 4>,<246 4>,
 718                                      <247 4>,<248 4>,<249 4>,<250 4>,<251 4>,
 719                                      <252 4>,<253 4>,<254 4>,<255 4>,<256 4>,
 720                                      <257 4>,<258 4>,<259 4>,<260 4>,<261 4>,
 721                                      <262 4>,<263 4>,<264 4>,<265 4>,<266 4>,
 722                                      <267 4>,<268 4>,<269 4>,<270 4>,<271 4>,
 723                                      <272 4>,<273 4>,<274 4>,<275 4>,<276 4>,
 724                                      <277 4>,<278 4>,<279 4>,<280 4>,<281 4>,
 725                                      <282 4>,<283 4>,<284 4>,<285 4>,<286 4>,
 726                                      <287 4>,<608 1>,<609 1>,<610 1>,<611 1>,
 727                                      <612 1>,<613 1>,<614 1>,<615 1>,<616 1>,
 728                                      <617 1>,<618 1>,<619 1>,<620 1>,<621 1>,
 729                                      <622 1>,<623 1>,<624 1>,<625 1>,<626 1>,
 730                                      <627 1>,<628 1>,<629 1>,<630 1>,<631 1>,
 731                                      <632 1>,<633 1>,<634 1>,<635 1>,<636 1>,
 732                                      <637 1>,<638 1>,<639 1>;
 733                         status = "disabled";
 734                 };
 735
 736                 pcie0: pcie@a0090000 {
 737                         compatible = "hisilicon,hip06-pcie-ecam";
 738                         reg = <0 0xb0000000 0 0x2000000>,
 739                               <0 0xa0090000 0 0x10000>;
 740                         bus-range = <0  31>;
 741                         msi-map = <0x0000 &its_dsa 0x0000 0x2000>;
 742                         msi-map-mask = <0xffff>;
 743                         #address-cells = <3>;
 744                         #size-cells = <2>;
 745                         device_type = "pci";
 746                         dma-coherent;
 747                         ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000>,
 748                                  <0x01000000 0 0 0 0xb7ff0000 0 0x10000>;
 749                         #interrupt-cells = <1>;
 750                         interrupt-map-mask = <0xf800 0 0 7>;
 751                         interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
 752                                         0x0 0 0 2 &mbigen_pcie0 650 4
 753                                         0x0 0 0 3 &mbigen_pcie0 650 4
 754                                         0x0 0 0 4 &mbigen_pcie0 650 4>;
 755                         status = "disabled";
 756                 };
 757
 758         };
 759
 760 };