1 // SPDX-License-Identifier: GPL-2.0-only
3 * dts file for Hisilicon D02 Development Board
5 * Copyright (C) 2014,2015 HiSilicon Ltd.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
17 compatible = "arm,psci-0.2";
86 compatible = "arm,cortex-a57";
88 enable-method = "psci";
89 next-level-cache = <&cluster0_l2>;
94 compatible = "arm,cortex-a57";
96 enable-method = "psci";
97 next-level-cache = <&cluster0_l2>;
102 compatible = "arm,cortex-a57";
104 enable-method = "psci";
105 next-level-cache = <&cluster0_l2>;
110 compatible = "arm,cortex-a57";
112 enable-method = "psci";
113 next-level-cache = <&cluster0_l2>;
118 compatible = "arm,cortex-a57";
120 enable-method = "psci";
121 next-level-cache = <&cluster1_l2>;
126 compatible = "arm,cortex-a57";
128 enable-method = "psci";
129 next-level-cache = <&cluster1_l2>;
134 compatible = "arm,cortex-a57";
136 enable-method = "psci";
137 next-level-cache = <&cluster1_l2>;
142 compatible = "arm,cortex-a57";
144 enable-method = "psci";
145 next-level-cache = <&cluster1_l2>;
150 compatible = "arm,cortex-a57";
152 enable-method = "psci";
153 next-level-cache = <&cluster2_l2>;
158 compatible = "arm,cortex-a57";
160 enable-method = "psci";
161 next-level-cache = <&cluster2_l2>;
166 compatible = "arm,cortex-a57";
168 enable-method = "psci";
169 next-level-cache = <&cluster2_l2>;
174 compatible = "arm,cortex-a57";
176 enable-method = "psci";
177 next-level-cache = <&cluster2_l2>;
182 compatible = "arm,cortex-a57";
184 enable-method = "psci";
185 next-level-cache = <&cluster3_l2>;
190 compatible = "arm,cortex-a57";
192 enable-method = "psci";
193 next-level-cache = <&cluster3_l2>;
198 compatible = "arm,cortex-a57";
200 enable-method = "psci";
201 next-level-cache = <&cluster3_l2>;
206 compatible = "arm,cortex-a57";
208 enable-method = "psci";
209 next-level-cache = <&cluster3_l2>;
212 cluster0_l2: l2-cache0 {
213 compatible = "cache";
218 cluster1_l2: l2-cache1 {
219 compatible = "cache";
224 cluster2_l2: l2-cache2 {
225 compatible = "cache";
230 cluster3_l2: l2-cache3 {
231 compatible = "cache";
237 gic: interrupt-controller@8d000000 {
238 compatible = "arm,gic-v3";
239 #interrupt-cells = <3>;
240 #address-cells = <2>;
243 interrupt-controller;
244 #redistributor-regions = <1>;
245 redistributor-stride = <0x0 0x30000>;
246 reg = <0x0 0x8d000000 0 0x10000>, /* GICD */
247 <0x0 0x8d100000 0 0x300000>, /* GICR */
248 <0x0 0xfe000000 0 0x10000>, /* GICC */
249 <0x0 0xfe010000 0 0x10000>, /* GICH */
250 <0x0 0xfe020000 0 0x10000>; /* GICV */
251 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
253 its_peri: msi-controller@8c000000 {
254 compatible = "arm,gic-v3-its";
257 reg = <0x0 0x8c000000 0x0 0x40000>;
260 its_m3: msi-controller@a3000000 {
261 compatible = "arm,gic-v3-its";
264 reg = <0x0 0xa3000000 0x0 0x40000>;
267 its_pcie: msi-controller@b7000000 {
268 compatible = "arm,gic-v3-its";
271 reg = <0x0 0xb7000000 0x0 0x40000>;
274 its_dsa: msi-controller@c6000000 {
275 compatible = "arm,gic-v3-its";
278 reg = <0x0 0xc6000000 0x0 0x40000>;
283 compatible = "arm,armv8-timer";
284 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
285 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
286 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
287 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
291 compatible = "arm,cortex-a57-pmu";
292 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
296 compatible = "simple-bus";
297 #address-cells = <2>;
301 refclk200mhz: refclk200mhz {
302 compatible = "fixed-clock";
304 clock-frequency = <200000000>;
307 uart0: serial@80300000 {
308 compatible = "snps,dw-apb-uart";
309 reg = <0x0 0x80300000 0x0 0x10000>;
310 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&refclk200mhz>, <&refclk200mhz>;
312 clock-names = "baudclk", "apb_pclk";
318 uart1: serial@80310000 {
319 compatible = "snps,dw-apb-uart";
320 reg = <0x0 0x80310000 0x0 0x10000>;
321 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&refclk200mhz>, <&refclk200mhz>;
323 clock-names = "baudclk", "apb_pclk";
329 lbc: local-bus@80380000 {
330 compatible = "hisilicon,hisi-localbus", "simple-bus";
331 reg = <0x0 0x80380000 0x0 0x10000>;
335 peri_gpio0: gpio@802e0000 {
336 #address-cells = <1>;
338 compatible = "snps,dw-apb-gpio";
339 reg = <0x0 0x802e0000 0x0 0x10000>;
342 porta: gpio-controller@0 {
343 compatible = "snps,dw-apb-gpio-port";
348 interrupt-controller;
349 #interrupt-cells = <2>;
350 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
354 peri_gpio1: gpio@802f0000 {
355 #address-cells = <1>;
357 compatible = "snps,dw-apb-gpio";
358 reg = <0x0 0x802f0000 0x0 0x10000>;
361 portb: gpio-controller@0 {
362 compatible = "snps,dw-apb-gpio-port";
367 interrupt-controller;
368 #interrupt-cells = <2>;
369 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;