arch/arm64/boot/dts/hisilicon/hi6220.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for Hisilicon Hi6220 SoC
   4  *
   5  * Copyright (C) 2015, Hisilicon Ltd.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
  10 #include <dt-bindings/clock/hi6220-clock.h>
  11 #include <dt-bindings/pinctrl/hisi.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "hisilicon,hi6220";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         psci {
  21                 compatible = "arm,psci-0.2";
  22                 method = "smc";
  23         };
  24
  25         cpus {
  26                 #address-cells = <2>;
  27                 #size-cells = <0>;
  28
  29                 cpu-map {
  30                         cluster0 {
  31                                 core0 {
  32                                         cpu = <&cpu0>;
  33                                 };
  34                                 core1 {
  35                                         cpu = <&cpu1>;
  36                                 };
  37                                 core2 {
  38                                         cpu = <&cpu2>;
  39                                 };
  40                                 core3 {
  41                                         cpu = <&cpu3>;
  42                                 };
  43                         };
  44                         cluster1 {
  45                                 core0 {
  46                                         cpu = <&cpu4>;
  47                                 };
  48                                 core1 {
  49                                         cpu = <&cpu5>;
  50                                 };
  51                                 core2 {
  52                                         cpu = <&cpu6>;
  53                                 };
  54                                 core3 {
  55                                         cpu = <&cpu7>;
  56                                 };
  57                         };
  58                 };
  59
  60                 idle-states {
  61                         entry-method = "psci";
  62
  63                         CPU_SLEEP: cpu-sleep {
  64                                 compatible = "arm,idle-state";
  65                                 local-timer-stop;
  66                                 arm,psci-suspend-param = <0x0010000>;
  67                                 entry-latency-us = <700>;
  68                                 exit-latency-us = <250>;
  69                                 min-residency-us = <1000>;
  70                         };
  71
  72                         CLUSTER_SLEEP: cluster-sleep {
  73                                 compatible = "arm,idle-state";
  74                                 local-timer-stop;
  75                                 arm,psci-suspend-param = <0x1010000>;
  76                                 entry-latency-us = <1000>;
  77                                 exit-latency-us = <700>;
  78                                 min-residency-us = <2700>;
  79                                 wakeup-latency-us = <1500>;
  80                         };
  81                 };
  82
  83                 cpu0: cpu@0 {
  84                         compatible = "arm,cortex-a53", "arm,armv8";
  85                         device_type = "cpu";
  86                         reg = <0x0 0x0>;
  87                         enable-method = "psci";
  88                         next-level-cache = <&CLUSTER0_L2>;
  89                         clocks = <&stub_clock 0>;
  90                         operating-points-v2 = <&cpu_opp_table>;
  91                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  92                         #cooling-cells = <2>; /* min followed by max */
  93                         dynamic-power-coefficient = <311>;
  94                 };
  95
  96                 cpu1: cpu@1 {
  97                         compatible = "arm,cortex-a53", "arm,armv8";
  98                         device_type = "cpu";
  99                         reg = <0x0 0x1>;
 100                         enable-method = "psci";
 101                         next-level-cache = <&CLUSTER0_L2>;
 102                         operating-points-v2 = <&cpu_opp_table>;
 103                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 104                         #cooling-cells = <2>; /* min followed by max */
 105                         dynamic-power-coefficient = <311>;
 106                 };
 107
 108                 cpu2: cpu@2 {
 109                         compatible = "arm,cortex-a53", "arm,armv8";
 110                         device_type = "cpu";
 111                         reg = <0x0 0x2>;
 112                         enable-method = "psci";
 113                         next-level-cache = <&CLUSTER0_L2>;
 114                         operating-points-v2 = <&cpu_opp_table>;
 115                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <311>;
 118                 };
 119
 120                 cpu3: cpu@3 {
 121                         compatible = "arm,cortex-a53", "arm,armv8";
 122                         device_type = "cpu";
 123                         reg = <0x0 0x3>;
 124                         enable-method = "psci";
 125                         next-level-cache = <&CLUSTER0_L2>;
 126                         operating-points-v2 = <&cpu_opp_table>;
 127                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 128                         #cooling-cells = <2>; /* min followed by max */
 129                         dynamic-power-coefficient = <311>;
 130                 };
 131
 132                 cpu4: cpu@100 {
 133                         compatible = "arm,cortex-a53", "arm,armv8";
 134                         device_type = "cpu";
 135                         reg = <0x0 0x100>;
 136                         enable-method = "psci";
 137                         next-level-cache = <&CLUSTER1_L2>;
 138                         operating-points-v2 = <&cpu_opp_table>;
 139                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 140                         #cooling-cells = <2>; /* min followed by max */
 141                         dynamic-power-coefficient = <311>;
 142                 };
 143
 144                 cpu5: cpu@101 {
 145                         compatible = "arm,cortex-a53", "arm,armv8";
 146                         device_type = "cpu";
 147                         reg = <0x0 0x101>;
 148                         enable-method = "psci";
 149                         next-level-cache = <&CLUSTER1_L2>;
 150                         operating-points-v2 = <&cpu_opp_table>;
 151                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 152                         #cooling-cells = <2>; /* min followed by max */
 153                         dynamic-power-coefficient = <311>;
 154                 };
 155
 156                 cpu6: cpu@102 {
 157                         compatible = "arm,cortex-a53", "arm,armv8";
 158                         device_type = "cpu";
 159                         reg = <0x0 0x102>;
 160                         enable-method = "psci";
 161                         next-level-cache = <&CLUSTER1_L2>;
 162                         operating-points-v2 = <&cpu_opp_table>;
 163                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 164                         #cooling-cells = <2>; /* min followed by max */
 165                         dynamic-power-coefficient = <311>;
 166                 };
 167
 168                 cpu7: cpu@103 {
 169                         compatible = "arm,cortex-a53", "arm,armv8";
 170                         device_type = "cpu";
 171                         reg = <0x0 0x103>;
 172                         enable-method = "psci";
 173                         next-level-cache = <&CLUSTER1_L2>;
 174                         operating-points-v2 = <&cpu_opp_table>;
 175                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 176                         #cooling-cells = <2>; /* min followed by max */
 177                         dynamic-power-coefficient = <311>;
 178                 };
 179
 180                 CLUSTER0_L2: l2-cache0 {
 181                         compatible = "cache";
 182                 };
 183
 184                 CLUSTER1_L2: l2-cache1 {
 185                         compatible = "cache";
 186                 };
 187         };
 188
 189         cpu_opp_table: cpu_opp_table {
 190                 compatible = "operating-points-v2";
 191                 opp-shared;
 192
 193                 opp00 {
 194                         opp-hz = /bits/ 64 <208000000>;
 195                         opp-microvolt = <1040000>;
 196                         clock-latency-ns = <500000>;
 197                 };
 198                 opp01 {
 199                         opp-hz = /bits/ 64 <432000000>;
 200                         opp-microvolt = <1040000>;
 201                         clock-latency-ns = <500000>;
 202                 };
 203                 opp02 {
 204                         opp-hz = /bits/ 64 <729000000>;
 205                         opp-microvolt = <1090000>;
 206                         clock-latency-ns = <500000>;
 207                 };
 208                 opp03 {
 209                         opp-hz = /bits/ 64 <960000000>;
 210                         opp-microvolt = <1180000>;
 211                         clock-latency-ns = <500000>;
 212                 };
 213                 opp04 {
 214                         opp-hz = /bits/ 64 <1200000000>;
 215                         opp-microvolt = <1330000>;
 216                         clock-latency-ns = <500000>;
 217                 };
 218         };
 219
 220         gic: interrupt-controller@f6801000 {
 221                 compatible = "arm,gic-400";
 222                 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
 223                       <0x0 0xf6802000 0 0x2000>, /* GICC */
 224                       <0x0 0xf6804000 0 0x2000>, /* GICH */
 225                       <0x0 0xf6806000 0 0x2000>; /* GICV */
 226                 #address-cells = <0>;
 227                 #interrupt-cells = <3>;
 228                 interrupt-controller;
 229                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 230         };
 231
 232         timer {
 233                 compatible = "arm,armv8-timer";
 234                 interrupt-parent = <&gic>;
 235                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 236                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 237                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 238                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 239         };
 240
 241         soc {
 242                 compatible = "simple-bus";
 243                 #address-cells = <2>;
 244                 #size-cells = <2>;
 245                 ranges;
 246
 247                 sram: sram@fff80000 {
 248                         compatible = "hisilicon,hi6220-sramctrl", "syscon";
 249                         reg = <0x0 0xfff80000 0x0 0x12000>;
 250                 };
 251
 252                 ao_ctrl: ao_ctrl@f7800000 {
 253                         compatible = "hisilicon,hi6220-aoctrl", "syscon";
 254                         reg = <0x0 0xf7800000 0x0 0x2000>;
 255                         #clock-cells = <1>;
 256                 };
 257
 258                 sys_ctrl: sys_ctrl@f7030000 {
 259                         compatible = "hisilicon,hi6220-sysctrl", "syscon";
 260                         reg = <0x0 0xf7030000 0x0 0x2000>;
 261                         #clock-cells = <1>;
 262                         #reset-cells = <1>;
 263                 };
 264
 265                 media_ctrl: media_ctrl@f4410000 {
 266                         compatible = "hisilicon,hi6220-mediactrl", "syscon";
 267                         reg = <0x0 0xf4410000 0x0 0x1000>;
 268                         #clock-cells = <1>;
 269                         #reset-cells = <1>;
 270                 };
 271
 272                 pm_ctrl: pm_ctrl@f7032000 {
 273                         compatible = "hisilicon,hi6220-pmctrl", "syscon";
 274                         reg = <0x0 0xf7032000 0x0 0x1000>;
 275                         #clock-cells = <1>;
 276                 };
 277
 278                 acpu_sctrl: acpu_sctrl@f6504000 {
 279                         compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
 280                         reg = <0x0 0xf6504000 0x0 0x1000>;
 281                         #clock-cells = <1>;
 282                 };
 283
 284                 medianoc_ade: medianoc_ade@f4520000 {
 285                         compatible = "syscon";
 286                         reg = <0x0 0xf4520000 0x0 0x4000>;
 287                 };
 288
 289                 stub_clock: stub_clock {
 290                         compatible = "hisilicon,hi6220-stub-clk";
 291                         hisilicon,hi6220-clk-sram = <&sram>;
 292                         #clock-cells = <1>;
 293                         mbox-names = "mbox-tx";
 294                         mboxes = <&mailbox 1 0 11>;
 295                 };
 296
 297                 uart0: uart@f8015000 {  /* console */
 298                         compatible = "arm,pl011", "arm,primecell";
 299                         reg = <0x0 0xf8015000 0x0 0x1000>;
 300                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 301                         clocks = <&ao_ctrl HI6220_UART0_PCLK>,
 302                                  <&ao_ctrl HI6220_UART0_PCLK>;
 303                         clock-names = "uartclk", "apb_pclk";
 304                 };
 305
 306                 uart1: uart@f7111000 {
 307                         compatible = "arm,pl011", "arm,primecell";
 308                         reg = <0x0 0xf7111000 0x0 0x1000>;
 309                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 310                         clocks = <&sys_ctrl HI6220_UART1_PCLK>,
 311                                  <&sys_ctrl HI6220_UART1_PCLK>;
 312                         clock-names = "uartclk", "apb_pclk";
 313                         pinctrl-names = "default";
 314                         pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
 315                         status = "disabled";
 316                 };
 317
 318                 uart2: uart@f7112000 {
 319                         compatible = "arm,pl011", "arm,primecell";
 320                         reg = <0x0 0xf7112000 0x0 0x1000>;
 321                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 322                         clocks = <&sys_ctrl HI6220_UART2_PCLK>,
 323                                  <&sys_ctrl HI6220_UART2_PCLK>;
 324                         clock-names = "uartclk", "apb_pclk";
 325                         pinctrl-names = "default";
 326                         pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
 327                         status = "disabled";
 328                 };
 329
 330                 uart3: uart@f7113000 {
 331                         compatible = "arm,pl011", "arm,primecell";
 332                         reg = <0x0 0xf7113000 0x0 0x1000>;
 333                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 334                         clocks = <&sys_ctrl HI6220_UART3_PCLK>,
 335                                  <&sys_ctrl HI6220_UART3_PCLK>;
 336                         clock-names = "uartclk", "apb_pclk";
 337                         pinctrl-names = "default";
 338                         pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
 339                         status = "disabled";
 340                 };
 341
 342                 uart4: uart@f7114000 {
 343                         compatible = "arm,pl011", "arm,primecell";
 344                         reg = <0x0 0xf7114000 0x0 0x1000>;
 345                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&sys_ctrl HI6220_UART4_PCLK>,
 347                                  <&sys_ctrl HI6220_UART4_PCLK>;
 348                         clock-names = "uartclk", "apb_pclk";
 349                         pinctrl-names = "default";
 350                         pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
 351                         status = "disabled";
 352                 };
 353
 354                 dma0: dma@f7370000 {
 355                         compatible = "hisilicon,k3-dma-1.0";
 356                         reg = <0x0 0xf7370000 0x0 0x1000>;
 357                         #dma-cells = <1>;
 358                         dma-channels = <15>;
 359                         dma-requests = <32>;
 360                         interrupts = <0 84 4>;
 361                         clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
 362                         dma-no-cci;
 363                         dma-type = "hi6220_dma";
 364                         status = "ok";
 365                 };
 366
 367                 dual_timer0: timer@f8008000 {
 368                         compatible = "arm,sp804", "arm,primecell";
 369                         reg = <0x0 0xf8008000 0x0 0x1000>;
 370                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 371                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 372                         clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
 373                                  <&ao_ctrl HI6220_TIMER0_PCLK>,
 374                                  <&ao_ctrl HI6220_TIMER0_PCLK>;
 375                         clock-names = "timer1", "timer2", "apb_pclk";
 376                 };
 377
 378                 rtc0: rtc@f8003000 {
 379                         compatible = "arm,pl031", "arm,primecell";
 380                         reg = <0x0 0xf8003000 0x0 0x1000>;
 381                         interrupts = <0 12 4>;
 382                         clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
 383                         clock-names = "apb_pclk";
 384                 };
 385
 386                 rtc1: rtc@f8004000 {
 387                         compatible = "arm,pl031", "arm,primecell";
 388                         reg = <0x0 0xf8004000 0x0 0x1000>;
 389                         interrupts = <0 8 4>;
 390                         clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
 391                         clock-names = "apb_pclk";
 392                 };
 393
 394                 pmx0: pinmux@f7010000 {
 395                         compatible = "pinctrl-single";
 396                         reg = <0x0 0xf7010000  0x0 0x27c>;
 397                         #address-cells = <1>;
 398                         #size-cells = <1>;
 399                         #pinctrl-cells = <1>;
 400                         #gpio-range-cells = <3>;
 401                         pinctrl-single,register-width = <32>;
 402                         pinctrl-single,function-mask = <7>;
 403                         pinctrl-single,gpio-range = <
 404                                 &range  80  8 MUX_M0 /* gpio  3: [0..7] */
 405                                 &range  88  8 MUX_M0 /* gpio  4: [0..7] */
 406                                 &range  96  8 MUX_M0 /* gpio  5: [0..7] */
 407                                 &range 104  8 MUX_M0 /* gpio  6: [0..7] */
 408                                 &range 112  8 MUX_M0 /* gpio  7: [0..7] */
 409                                 &range 120  2 MUX_M0 /* gpio  8: [0..1] */
 410                                 &range   2  6 MUX_M1 /* gpio  8: [2..7] */
 411                                 &range   8  8 MUX_M1 /* gpio  9: [0..7] */
 412                                 &range   0  1 MUX_M1 /* gpio 10: [0]    */
 413                                 &range  16  7 MUX_M1 /* gpio 10: [1..7] */
 414                                 &range  23  3 MUX_M1 /* gpio 11: [0..2] */
 415                                 &range  28  5 MUX_M1 /* gpio 11: [3..7] */
 416                                 &range  33  3 MUX_M1 /* gpio 12: [0..2] */
 417                                 &range  43  5 MUX_M1 /* gpio 12: [3..7] */
 418                                 &range  48  8 MUX_M1 /* gpio 13: [0..7] */
 419                                 &range  56  8 MUX_M1 /* gpio 14: [0..7] */
 420                                 &range  74  6 MUX_M1 /* gpio 15: [0..5] */
 421                                 &range 122  1 MUX_M1 /* gpio 15: [6]    */
 422                                 &range 126  1 MUX_M1 /* gpio 15: [7]    */
 423                                 &range 127  8 MUX_M1 /* gpio 16: [0..7] */
 424                                 &range 135  8 MUX_M1 /* gpio 17: [0..7] */
 425                                 &range 143  8 MUX_M1 /* gpio 18: [0..7] */
 426                                 &range 151  8 MUX_M1 /* gpio 19: [0..7] */
 427                         >;
 428                         range: gpio-range {
 429                                 #pinctrl-single,gpio-range-cells = <3>;
 430                         };
 431                 };
 432
 433                 pmx1: pinmux@f7010800 {
 434                         compatible = "pinconf-single";
 435                         reg = <0x0 0xf7010800 0x0 0x28c>;
 436                         #address-cells = <1>;
 437                         #size-cells = <1>;
 438                         #pinctrl-cells = <1>;
 439                         pinctrl-single,register-width = <32>;
 440                 };
 441
 442                 pmx2: pinmux@f8001800 {
 443                         compatible = "pinconf-single";
 444                         reg = <0x0 0xf8001800 0x0 0x78>;
 445                         #address-cells = <1>;
 446                         #size-cells = <1>;
 447                         #pinctrl-cells = <1>;
 448                         pinctrl-single,register-width = <32>;
 449                 };
 450
 451                 gpio0: gpio@f8011000 {
 452                         compatible = "arm,pl061", "arm,primecell";
 453                         reg = <0x0 0xf8011000 0x0 0x1000>;
 454                         interrupts = <0 52 0x4>;
 455                         gpio-controller;
 456                         #gpio-cells = <2>;
 457                         interrupt-controller;
 458                         #interrupt-cells = <2>;
 459                         clocks = <&ao_ctrl 2>;
 460                         clock-names = "apb_pclk";
 461                 };
 462
 463                 gpio1: gpio@f8012000 {
 464                         compatible = "arm,pl061", "arm,primecell";
 465                         reg = <0x0 0xf8012000 0x0 0x1000>;
 466                         interrupts = <0 53 0x4>;
 467                         gpio-controller;
 468                         #gpio-cells = <2>;
 469                         interrupt-controller;
 470                         #interrupt-cells = <2>;
 471                         clocks = <&ao_ctrl 2>;
 472                         clock-names = "apb_pclk";
 473                 };
 474
 475                 gpio2: gpio@f8013000 {
 476                         compatible = "arm,pl061", "arm,primecell";
 477                         reg = <0x0 0xf8013000 0x0 0x1000>;
 478                         interrupts = <0 54 0x4>;
 479                         gpio-controller;
 480                         #gpio-cells = <2>;
 481                         interrupt-controller;
 482                         #interrupt-cells = <2>;
 483                         clocks = <&ao_ctrl 2>;
 484                         clock-names = "apb_pclk";
 485                 };
 486
 487                 gpio3: gpio@f8014000 {
 488                         compatible = "arm,pl061", "arm,primecell";
 489                         reg = <0x0 0xf8014000 0x0 0x1000>;
 490                         interrupts = <0 55 0x4>;
 491                         gpio-controller;
 492                         #gpio-cells = <2>;
 493                         gpio-ranges = <&pmx0 0 80 8>;
 494                         interrupt-controller;
 495                         #interrupt-cells = <2>;
 496                         clocks = <&ao_ctrl 2>;
 497                         clock-names = "apb_pclk";
 498                 };
 499
 500                 gpio4: gpio@f7020000 {
 501                         compatible = "arm,pl061", "arm,primecell";
 502                         reg = <0x0 0xf7020000 0x0 0x1000>;
 503                         interrupts = <0 56 0x4>;
 504                         gpio-controller;
 505                         #gpio-cells = <2>;
 506                         gpio-ranges = <&pmx0 0 88 8>;
 507                         interrupt-controller;
 508                         #interrupt-cells = <2>;
 509                         clocks = <&ao_ctrl 2>;
 510                         clock-names = "apb_pclk";
 511                 };
 512
 513                 gpio5: gpio@f7021000 {
 514                         compatible = "arm,pl061", "arm,primecell";
 515                         reg = <0x0 0xf7021000 0x0 0x1000>;
 516                         interrupts = <0 57 0x4>;
 517                         gpio-controller;
 518                         #gpio-cells = <2>;
 519                         gpio-ranges = <&pmx0 0 96 8>;
 520                         interrupt-controller;
 521                         #interrupt-cells = <2>;
 522                         clocks = <&ao_ctrl 2>;
 523                         clock-names = "apb_pclk";
 524                 };
 525
 526                 gpio6: gpio@f7022000 {
 527                         compatible = "arm,pl061", "arm,primecell";
 528                         reg = <0x0 0xf7022000 0x0 0x1000>;
 529                         interrupts = <0 58 0x4>;
 530                         gpio-controller;
 531                         #gpio-cells = <2>;
 532                         gpio-ranges = <&pmx0 0 104 8>;
 533                         interrupt-controller;
 534                         #interrupt-cells = <2>;
 535                         clocks = <&ao_ctrl 2>;
 536                         clock-names = "apb_pclk";
 537                 };
 538
 539                 gpio7: gpio@f7023000 {
 540                         compatible = "arm,pl061", "arm,primecell";
 541                         reg = <0x0 0xf7023000 0x0 0x1000>;
 542                         interrupts = <0 59 0x4>;
 543                         gpio-controller;
 544                         #gpio-cells = <2>;
 545                         gpio-ranges = <&pmx0 0 112 8>;
 546                         interrupt-controller;
 547                         #interrupt-cells = <2>;
 548                         clocks = <&ao_ctrl 2>;
 549                         clock-names = "apb_pclk";
 550                 };
 551
 552                 gpio8: gpio@f7024000 {
 553                         compatible = "arm,pl061", "arm,primecell";
 554                         reg = <0x0 0xf7024000 0x0 0x1000>;
 555                         interrupts = <0 60 0x4>;
 556                         gpio-controller;
 557                         #gpio-cells = <2>;
 558                         gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
 559                         interrupt-controller;
 560                         #interrupt-cells = <2>;
 561                         clocks = <&ao_ctrl 2>;
 562                         clock-names = "apb_pclk";
 563                 };
 564
 565                 gpio9: gpio@f7025000 {
 566                         compatible = "arm,pl061", "arm,primecell";
 567                         reg = <0x0 0xf7025000 0x0 0x1000>;
 568                         interrupts = <0 61 0x4>;
 569                         gpio-controller;
 570                         #gpio-cells = <2>;
 571                         gpio-ranges = <&pmx0 0 8 8>;
 572                         interrupt-controller;
 573                         #interrupt-cells = <2>;
 574                         clocks = <&ao_ctrl 2>;
 575                         clock-names = "apb_pclk";
 576                 };
 577
 578                 gpio10: gpio@f7026000 {
 579                         compatible = "arm,pl061", "arm,primecell";
 580                         reg = <0x0 0xf7026000 0x0 0x1000>;
 581                         interrupts = <0 62 0x4>;
 582                         gpio-controller;
 583                         #gpio-cells = <2>;
 584                         gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
 585                         interrupt-controller;
 586                         #interrupt-cells = <2>;
 587                         clocks = <&ao_ctrl 2>;
 588                         clock-names = "apb_pclk";
 589                 };
 590
 591                 gpio11: gpio@f7027000 {
 592                         compatible = "arm,pl061", "arm,primecell";
 593                         reg = <0x0 0xf7027000 0x0 0x1000>;
 594                         interrupts = <0 63 0x4>;
 595                         gpio-controller;
 596                         #gpio-cells = <2>;
 597                         gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
 598                         interrupt-controller;
 599                         #interrupt-cells = <2>;
 600                         clocks = <&ao_ctrl 2>;
 601                         clock-names = "apb_pclk";
 602                 };
 603
 604                 gpio12: gpio@f7028000 {
 605                         compatible = "arm,pl061", "arm,primecell";
 606                         reg = <0x0 0xf7028000 0x0 0x1000>;
 607                         interrupts = <0 64 0x4>;
 608                         gpio-controller;
 609                         #gpio-cells = <2>;
 610                         gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
 611                         interrupt-controller;
 612                         #interrupt-cells = <2>;
 613                         clocks = <&ao_ctrl 2>;
 614                         clock-names = "apb_pclk";
 615                 };
 616
 617                 gpio13: gpio@f7029000 {
 618                         compatible = "arm,pl061", "arm,primecell";
 619                         reg = <0x0 0xf7029000 0x0 0x1000>;
 620                         interrupts = <0 65 0x4>;
 621                         gpio-controller;
 622                         #gpio-cells = <2>;
 623                         gpio-ranges = <&pmx0 0 48 8>;
 624                         interrupt-controller;
 625                         #interrupt-cells = <2>;
 626                         clocks = <&ao_ctrl 2>;
 627                         clock-names = "apb_pclk";
 628                 };
 629
 630                 gpio14: gpio@f702a000 {
 631                         compatible = "arm,pl061", "arm,primecell";
 632                         reg = <0x0 0xf702a000 0x0 0x1000>;
 633                         interrupts = <0 66 0x4>;
 634                         gpio-controller;
 635                         #gpio-cells = <2>;
 636                         gpio-ranges = <&pmx0 0 56 8>;
 637                         interrupt-controller;
 638                         #interrupt-cells = <2>;
 639                         clocks = <&ao_ctrl 2>;
 640                         clock-names = "apb_pclk";
 641                 };
 642
 643                 gpio15: gpio@f702b000 {
 644                         compatible = "arm,pl061", "arm,primecell";
 645                         reg = <0x0 0xf702b000 0x0 0x1000>;
 646                         interrupts = <0 67 0x4>;
 647                         gpio-controller;
 648                         #gpio-cells = <2>;
 649                         gpio-ranges = <
 650                                 &pmx0 0 74 6
 651                                 &pmx0 6 122 1
 652                                 &pmx0 7 126 1
 653                         >;
 654                         interrupt-controller;
 655                         #interrupt-cells = <2>;
 656                         clocks = <&ao_ctrl 2>;
 657                         clock-names = "apb_pclk";
 658                 };
 659
 660                 gpio16: gpio@f702c000 {
 661                         compatible = "arm,pl061", "arm,primecell";
 662                         reg = <0x0 0xf702c000 0x0 0x1000>;
 663                         interrupts = <0 68 0x4>;
 664                         gpio-controller;
 665                         #gpio-cells = <2>;
 666                         gpio-ranges = <&pmx0 0 127 8>;
 667                         interrupt-controller;
 668                         #interrupt-cells = <2>;
 669                         clocks = <&ao_ctrl 2>;
 670                         clock-names = "apb_pclk";
 671                 };
 672
 673                 gpio17: gpio@f702d000 {
 674                         compatible = "arm,pl061", "arm,primecell";
 675                         reg = <0x0 0xf702d000 0x0 0x1000>;
 676                         interrupts = <0 69 0x4>;
 677                         gpio-controller;
 678                         #gpio-cells = <2>;
 679                         gpio-ranges = <&pmx0 0 135 8>;
 680                         interrupt-controller;
 681                         #interrupt-cells = <2>;
 682                         clocks = <&ao_ctrl 2>;
 683                         clock-names = "apb_pclk";
 684                 };
 685
 686                 gpio18: gpio@f702e000 {
 687                         compatible = "arm,pl061", "arm,primecell";
 688                         reg = <0x0 0xf702e000 0x0 0x1000>;
 689                         interrupts = <0 70 0x4>;
 690                         gpio-controller;
 691                         #gpio-cells = <2>;
 692                         gpio-ranges = <&pmx0 0 143 8>;
 693                         interrupt-controller;
 694                         #interrupt-cells = <2>;
 695                         clocks = <&ao_ctrl 2>;
 696                         clock-names = "apb_pclk";
 697                 };
 698
 699                 gpio19: gpio@f702f000 {
 700                         compatible = "arm,pl061", "arm,primecell";
 701                         reg = <0x0 0xf702f000 0x0 0x1000>;
 702                         interrupts = <0 71 0x4>;
 703                         gpio-controller;
 704                         #gpio-cells = <2>;
 705                         gpio-ranges = <&pmx0 0 151 8>;
 706                         interrupt-controller;
 707                         #interrupt-cells = <2>;
 708                         clocks = <&ao_ctrl 2>;
 709                         clock-names = "apb_pclk";
 710                 };
 711
 712                 spi0: spi@f7106000 {
 713                         compatible = "arm,pl022", "arm,primecell";
 714                         reg = <0x0 0xf7106000 0x0 0x1000>;
 715                         interrupts = <0 50 4>;
 716                         bus-id = <0>;
 717                         enable-dma = <0>;
 718                         clocks = <&sys_ctrl HI6220_SPI_CLK>;
 719                         clock-names = "apb_pclk";
 720                         pinctrl-names = "default";
 721                         pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
 722                         num-cs = <1>;
 723                         cs-gpios = <&gpio6 2 0>;
 724                         status = "disabled";
 725                 };
 726
 727                 i2c0: i2c@f7100000 {
 728                         compatible = "snps,designware-i2c";
 729                         reg = <0x0 0xf7100000 0x0 0x1000>;
 730                         interrupts = <0 44 4>;
 731                         clocks = <&sys_ctrl HI6220_I2C0_CLK>;
 732                         i2c-sda-hold-time-ns = <300>;
 733                         pinctrl-names = "default";
 734                         pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
 735                         status = "disabled";
 736                 };
 737
 738                 i2c1: i2c@f7101000 {
 739                         compatible = "snps,designware-i2c";
 740                         reg = <0x0 0xf7101000 0x0 0x1000>;
 741                         clocks = <&sys_ctrl HI6220_I2C1_CLK>;
 742                         interrupts = <0 45 4>;
 743                         i2c-sda-hold-time-ns = <300>;
 744                         pinctrl-names = "default";
 745                         pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
 746                         status = "disabled";
 747                 };
 748
 749                 i2c2: i2c@f7102000 {
 750                         compatible = "snps,designware-i2c";
 751                         reg = <0x0 0xf7102000 0x0 0x1000>;
 752                         clocks = <&sys_ctrl HI6220_I2C2_CLK>;
 753                         interrupts = <0 46 4>;
 754                         i2c-sda-hold-time-ns = <300>;
 755                         pinctrl-names = "default";
 756                         pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
 757                         status = "disabled";
 758                 };
 759
 760                 usb_phy: usbphy {
 761                         compatible = "hisilicon,hi6220-usb-phy";
 762                         #phy-cells = <0>;
 763                         phy-supply = <&reg_5v_hub>;
 764                         hisilicon,peripheral-syscon = <&sys_ctrl>;
 765                 };
 766
 767                 usb: usb@f72c0000 {
 768                         compatible = "hisilicon,hi6220-usb";
 769                         reg = <0x0 0xf72c0000 0x0 0x40000>;
 770                         phys = <&usb_phy>;
 771                         phy-names = "usb2-phy";
 772                         clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
 773                         clock-names = "otg";
 774                         dr_mode = "otg";
 775                         g-rx-fifo-size = <512>;
 776                         g-np-tx-fifo-size = <128>;
 777                         g-tx-fifo-size = <128 128 128 128 128 128 128 128
 778                                            16  16  16  16  16  16  16>;
 779                         interrupts = <0 77 0x4>;
 780                 };
 781
 782                 mailbox: mailbox@f7510000 {
 783                         compatible = "hisilicon,hi6220-mbox";
 784                         reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
 785                               <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
 786                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 787                         #mbox-cells = <3>;
 788                 };
 789
 790                 dwmmc_0: dwmmc0@f723d000 {
 791                         compatible = "hisilicon,hi6220-dw-mshc";
 792                         reg = <0x0 0xf723d000 0x0 0x1000>;
 793                         interrupts = <0x0 0x48 0x4>;
 794                         clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
 795                         clock-names = "ciu", "biu";
 796                         resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
 797                         reset-names = "reset";
 798                         pinctrl-names = "default";
 799                         pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
 800                                      &emmc_cfg_func &emmc_rst_cfg_func>;
 801                 };
 802
 803                 dwmmc_1: dwmmc1@f723e000 {
 804                         compatible = "hisilicon,hi6220-dw-mshc";
 805                         hisilicon,peripheral-syscon = <&ao_ctrl>;
 806                         reg = <0x0 0xf723e000 0x0 0x1000>;
 807                         interrupts = <0x0 0x49 0x4>;
 808                         #address-cells = <0x1>;
 809                         #size-cells = <0x0>;
 810                         clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
 811                         clock-names = "ciu", "biu";
 812                         resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
 813                         reset-names = "reset";
 814                         pinctrl-names = "default", "idle";
 815                         pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
 816                         pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
 817                 };
 818
 819                 dwmmc_2: dwmmc2@f723f000 {
 820                         compatible = "hisilicon,hi6220-dw-mshc";
 821                         reg = <0x0 0xf723f000 0x0 0x1000>;
 822                         interrupts = <0x0 0x4a 0x4>;
 823                         clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
 824                         clock-names = "ciu", "biu";
 825                         resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
 826                         reset-names = "reset";
 827                         pinctrl-names = "default", "idle";
 828                         pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
 829                         pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
 830                 };
 831
 832                 watchdog0: watchdog@f8005000 {
 833                         compatible = "arm,sp805-wdt", "arm,primecell";
 834                         reg = <0x0 0xf8005000 0x0 0x1000>;
 835                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 836                         clocks = <&ao_ctrl HI6220_WDT0_PCLK>;
 837                         clock-names = "apb_pclk";
 838                 };
 839
 840                 tsensor: tsensor@0,f7030700 {
 841                         compatible = "hisilicon,tsensor";
 842                         reg = <0x0 0xf7030700 0x0 0x1000>;
 843                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 844                         clocks = <&sys_ctrl 22>;
 845                         clock-names = "thermal_clk";
 846                         #thermal-sensor-cells = <1>;
 847                 };
 848
 849                 i2s0: i2s@f7118000{
 850                         compatible = "hisilicon,hi6210-i2s";
 851                         reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
 852                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
 853                         clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
 854                                  <&sys_ctrl HI6220_BBPPLL0_DIV>;
 855                         clock-names = "dacodec", "i2s-base";
 856                         dmas = <&dma0 15 &dma0 14>;
 857                         dma-names = "rx", "tx";
 858                         hisilicon,sysctrl-syscon = <&sys_ctrl>;
 859                         #sound-dai-cells = <1>;
 860                 };
 861
 862                 thermal-zones {
 863
 864                         cls0: cls0 {
 865                                 polling-delay = <1000>;
 866                                 polling-delay-passive = <100>;
 867                                 sustainable-power = <3326>;
 868
 869                                 /* sensor ID */
 870                                 thermal-sensors = <&tsensor 2>;
 871
 872                                 trips {
 873                                         threshold: trip-point@0 {
 874                                                 temperature = <65000>;
 875                                                 hysteresis = <0>;
 876                                                 type = "passive";
 877                                         };
 878
 879                                         target: trip-point@1 {
 880                                                 temperature = <75000>;
 881                                                 hysteresis = <0>;
 882                                                 type = "passive";
 883                                         };
 884                                 };
 885
 886                                 cooling-maps {
 887                                         map0 {
 888                                                 trip = <&target>;
 889                                                 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 890                                         };
 891                                 };
 892                         };
 893                 };
 894
 895                 ade: ade@f4100000 {
 896                         compatible = "hisilicon,hi6220-ade";
 897                         reg = <0x0 0xf4100000 0x0 0x7800>;
 898                         reg-names = "ade_base";
 899                         hisilicon,noc-syscon = <&medianoc_ade>;
 900                         resets = <&media_ctrl MEDIA_ADE>;
 901                         interrupts = <0 115 4>; /* ldi interrupt */
 902
 903                         clocks = <&media_ctrl HI6220_ADE_CORE>,
 904                                  <&media_ctrl HI6220_CODEC_JPEG>,
 905                                  <&media_ctrl HI6220_ADE_PIX_SRC>;
 906                         /*clock name*/
 907                         clock-names  = "clk_ade_core",
 908                                        "clk_codec_jpeg",
 909                                        "clk_ade_pix";
 910
 911                         assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
 912                                 <&media_ctrl HI6220_CODEC_JPEG>;
 913                         assigned-clock-rates = <360000000>, <288000000>;
 914                         dma-coherent;
 915                         status = "disabled";
 916
 917                         port {
 918                                 ade_out: endpoint {
 919                                         remote-endpoint = <&dsi_in>;
 920                                 };
 921                         };
 922                 };
 923
 924                 dsi: dsi@f4107800 {
 925                         compatible = "hisilicon,hi6220-dsi";
 926                         reg = <0x0 0xf4107800 0x0 0x100>;
 927                         clocks = <&media_ctrl  HI6220_DSI_PCLK>;
 928                         clock-names = "pclk";
 929                         status = "disabled";
 930
 931                         ports {
 932                                 #address-cells = <1>;
 933                                 #size-cells = <0>;
 934
 935                                 /* 0 for input port */
 936                                 port@0 {
 937                                         reg = <0>;
 938                                         dsi_in: endpoint {
 939                                                 remote-endpoint = <&ade_out>;
 940                                         };
 941                                 };
 942                         };
 943                 };
 944
 945                 debug@f6590000 {
 946                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 947                         reg = <0 0xf6590000 0 0x1000>;
 948                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 949                         clock-names = "apb_pclk";
 950                         cpu = <&cpu0>;
 951                 };
 952
 953                 debug@f6592000 {
 954                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 955                         reg = <0 0xf6592000 0 0x1000>;
 956                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 957                         clock-names = "apb_pclk";
 958                         cpu = <&cpu1>;
 959                 };
 960
 961                 debug@f6594000 {
 962                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 963                         reg = <0 0xf6594000 0 0x1000>;
 964                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 965                         clock-names = "apb_pclk";
 966                         cpu = <&cpu2>;
 967                 };
 968
 969                 debug@f6596000 {
 970                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 971                         reg = <0 0xf6596000 0 0x1000>;
 972                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 973                         clock-names = "apb_pclk";
 974                         cpu = <&cpu3>;
 975                 };
 976
 977                 debug@f65d0000 {
 978                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 979                         reg = <0 0xf65d0000 0 0x1000>;
 980                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 981                         clock-names = "apb_pclk";
 982                         cpu = <&cpu4>;
 983                 };
 984
 985                 debug@f65d2000 {
 986                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 987                         reg = <0 0xf65d2000 0 0x1000>;
 988                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 989                         clock-names = "apb_pclk";
 990                         cpu = <&cpu5>;
 991                 };
 992
 993                 debug@f65d4000 {
 994                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 995                         reg = <0 0xf65d4000 0 0x1000>;
 996                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 997                         clock-names = "apb_pclk";
 998                         cpu = <&cpu6>;
 999                 };
1000
1001                 debug@f65d6000 {
1002                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1003                         reg = <0 0xf65d6000 0 0x1000>;
1004                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1005                         clock-names = "apb_pclk";
1006                         cpu = <&cpu7>;
1007                 };
1008         };
1009 };
1010
1011 #include "hi6220-coresight.dtsi"