1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Hisilicon Hi3660 SoC
5 * Copyright (C) 2016, HiSilicon Ltd.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/hi3660-clock.h>
10 #include <dt-bindings/thermal/thermal.h>
13 compatible = "hisilicon,hi3660";
14 interrupt-parent = <&gic>;
19 compatible = "arm,psci-0.2";
59 compatible = "arm,cortex-a53";
62 enable-method = "psci";
63 next-level-cache = <&A53_L2>;
64 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
65 capacity-dmips-mhz = <592>;
66 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
67 operating-points-v2 = <&cluster0_opp>;
69 dynamic-power-coefficient = <110>;
73 compatible = "arm,cortex-a53";
76 enable-method = "psci";
77 next-level-cache = <&A53_L2>;
78 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
79 capacity-dmips-mhz = <592>;
80 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
81 operating-points-v2 = <&cluster0_opp>;
86 compatible = "arm,cortex-a53";
89 enable-method = "psci";
90 next-level-cache = <&A53_L2>;
91 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
92 capacity-dmips-mhz = <592>;
93 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
94 operating-points-v2 = <&cluster0_opp>;
99 compatible = "arm,cortex-a53";
102 enable-method = "psci";
103 next-level-cache = <&A53_L2>;
104 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
105 capacity-dmips-mhz = <592>;
106 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
107 operating-points-v2 = <&cluster0_opp>;
108 #cooling-cells = <2>;
112 compatible = "arm,cortex-a73";
115 enable-method = "psci";
116 next-level-cache = <&A73_L2>;
117 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
118 capacity-dmips-mhz = <1024>;
119 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
120 operating-points-v2 = <&cluster1_opp>;
121 #cooling-cells = <2>;
122 dynamic-power-coefficient = <550>;
126 compatible = "arm,cortex-a73";
129 enable-method = "psci";
130 next-level-cache = <&A73_L2>;
131 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
132 capacity-dmips-mhz = <1024>;
133 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
134 operating-points-v2 = <&cluster1_opp>;
135 #cooling-cells = <2>;
139 compatible = "arm,cortex-a73";
142 enable-method = "psci";
143 next-level-cache = <&A73_L2>;
144 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
145 capacity-dmips-mhz = <1024>;
146 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
147 operating-points-v2 = <&cluster1_opp>;
148 #cooling-cells = <2>;
152 compatible = "arm,cortex-a73";
155 enable-method = "psci";
156 next-level-cache = <&A73_L2>;
157 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
158 capacity-dmips-mhz = <1024>;
159 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
160 operating-points-v2 = <&cluster1_opp>;
161 #cooling-cells = <2>;
165 entry-method = "psci";
167 CPU_SLEEP_0: cpu-sleep-0 {
168 compatible = "arm,idle-state";
170 arm,psci-suspend-param = <0x0010000>;
171 entry-latency-us = <400>;
172 exit-latency-us = <650>;
173 min-residency-us = <1500>;
175 CLUSTER_SLEEP_0: cluster-sleep-0 {
176 compatible = "arm,idle-state";
178 arm,psci-suspend-param = <0x1010000>;
179 entry-latency-us = <500>;
180 exit-latency-us = <1600>;
181 min-residency-us = <3500>;
185 CPU_SLEEP_1: cpu-sleep-1 {
186 compatible = "arm,idle-state";
188 arm,psci-suspend-param = <0x0010000>;
189 entry-latency-us = <400>;
190 exit-latency-us = <550>;
191 min-residency-us = <1500>;
194 CLUSTER_SLEEP_1: cluster-sleep-1 {
195 compatible = "arm,idle-state";
197 arm,psci-suspend-param = <0x1010000>;
198 entry-latency-us = <800>;
199 exit-latency-us = <2900>;
200 min-residency-us = <3500>;
205 compatible = "cache";
211 compatible = "cache";
217 cluster0_opp: opp-table-0 {
218 compatible = "operating-points-v2";
222 opp-hz = /bits/ 64 <533000000>;
223 opp-microvolt = <700000>;
224 clock-latency-ns = <300000>;
228 opp-hz = /bits/ 64 <999000000>;
229 opp-microvolt = <800000>;
230 clock-latency-ns = <300000>;
234 opp-hz = /bits/ 64 <1402000000>;
235 opp-microvolt = <900000>;
236 clock-latency-ns = <300000>;
240 opp-hz = /bits/ 64 <1709000000>;
241 opp-microvolt = <1000000>;
242 clock-latency-ns = <300000>;
246 opp-hz = /bits/ 64 <1844000000>;
247 opp-microvolt = <1100000>;
248 clock-latency-ns = <300000>;
252 cluster1_opp: opp-table-1 {
253 compatible = "operating-points-v2";
257 opp-hz = /bits/ 64 <903000000>;
258 opp-microvolt = <700000>;
259 clock-latency-ns = <300000>;
263 opp-hz = /bits/ 64 <1421000000>;
264 opp-microvolt = <800000>;
265 clock-latency-ns = <300000>;
269 opp-hz = /bits/ 64 <1805000000>;
270 opp-microvolt = <900000>;
271 clock-latency-ns = <300000>;
275 opp-hz = /bits/ 64 <2112000000>;
276 opp-microvolt = <1000000>;
277 clock-latency-ns = <300000>;
281 opp-hz = /bits/ 64 <2362000000>;
282 opp-microvolt = <1100000>;
283 clock-latency-ns = <300000>;
287 gic: interrupt-controller@e82b0000 {
288 compatible = "arm,gic-400";
289 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
290 <0x0 0xe82b2000 0 0x2000>, /* GICC */
291 <0x0 0xe82b4000 0 0x2000>, /* GICH */
292 <0x0 0xe82b6000 0 0x2000>; /* GICV */
293 #address-cells = <0>;
294 #interrupt-cells = <3>;
295 interrupt-controller;
296 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
297 IRQ_TYPE_LEVEL_HIGH)>;
301 compatible = "arm,cortex-a53-pmu";
302 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
306 interrupt-affinity = <&cpu0>,
313 compatible = "arm,cortex-a73-pmu";
314 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
318 interrupt-affinity = <&cpu4>,
325 compatible = "arm,armv8-timer";
326 interrupt-parent = <&gic>;
327 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
328 IRQ_TYPE_LEVEL_LOW)>,
329 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
330 IRQ_TYPE_LEVEL_LOW)>,
331 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
332 IRQ_TYPE_LEVEL_LOW)>,
333 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
334 IRQ_TYPE_LEVEL_LOW)>;
338 compatible = "simple-bus";
339 #address-cells = <2>;
343 crg_ctrl: crg_ctrl@fff35000 {
344 compatible = "hisilicon,hi3660-crgctrl", "syscon";
345 reg = <0x0 0xfff35000 0x0 0x1000>;
349 crg_rst: crg_rst_controller {
350 compatible = "hisilicon,hi3660-reset";
352 hisi,rst-syscon = <&crg_ctrl>;
356 pctrl: pctrl@e8a09000 {
357 compatible = "hisilicon,hi3660-pctrl", "syscon";
358 reg = <0x0 0xe8a09000 0x0 0x2000>;
362 pmuctrl: crg_ctrl@fff34000 {
363 compatible = "hisilicon,hi3660-pmuctrl", "syscon";
364 reg = <0x0 0xfff34000 0x0 0x1000>;
368 sctrl: sctrl@fff0a000 {
369 compatible = "hisilicon,hi3660-sctrl", "syscon";
370 reg = <0x0 0xfff0a000 0x0 0x1000>;
374 iomcu: iomcu@ffd7e000 {
375 compatible = "hisilicon,hi3660-iomcu", "syscon";
376 reg = <0x0 0xffd7e000 0x0 0x1000>;
382 compatible = "hisilicon,hi3660-reset";
383 hisi,rst-syscon = <&iomcu>;
387 mailbox: mailbox@e896b000 {
388 compatible = "hisilicon,hi3660-mbox";
389 reg = <0x0 0xe896b000 0x0 0x1000>;
390 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
395 stub_clock: stub_clock@e896b500 {
396 compatible = "hisilicon,hi3660-stub-clk";
397 reg = <0x0 0xe896b500 0x0 0x0100>;
399 mboxes = <&mailbox 13 3 0>;
402 dual_timer0: timer@fff14000 {
403 compatible = "arm,sp804", "arm,primecell";
404 reg = <0x0 0xfff14000 0x0 0x1000>;
405 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&crg_ctrl HI3660_OSC32K>,
408 <&crg_ctrl HI3660_OSC32K>,
409 <&crg_ctrl HI3660_OSC32K>;
410 clock-names = "timer1", "timer2", "apb_pclk";
414 compatible = "snps,designware-i2c";
415 reg = <0x0 0xffd71000 0x0 0x1000>;
416 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
417 #address-cells = <1>;
419 clock-frequency = <400000>;
420 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
421 resets = <&iomcu_rst 0x20 3>;
422 pinctrl-names = "default";
423 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
428 compatible = "snps,designware-i2c";
429 reg = <0x0 0xffd72000 0x0 0x1000>;
430 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
431 #address-cells = <1>;
433 clock-frequency = <400000>;
434 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
435 resets = <&iomcu_rst 0x20 4>;
436 pinctrl-names = "default";
437 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
442 compatible = "snps,designware-i2c";
443 reg = <0x0 0xfdf0c000 0x0 0x1000>;
444 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
445 #address-cells = <1>;
447 clock-frequency = <400000>;
448 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
449 resets = <&crg_rst 0x78 7>;
450 pinctrl-names = "default";
451 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
456 compatible = "snps,designware-i2c";
457 reg = <0x0 0xfdf0b000 0x0 0x1000>;
458 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
459 #address-cells = <1>;
461 clock-frequency = <400000>;
462 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
463 resets = <&crg_rst 0x60 14>;
464 pinctrl-names = "default";
465 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
469 uart0: serial@fdf02000 {
470 compatible = "arm,pl011", "arm,primecell";
471 reg = <0x0 0xfdf02000 0x0 0x1000>;
472 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
474 <&crg_ctrl HI3660_PCLK>;
475 clock-names = "uartclk", "apb_pclk";
476 pinctrl-names = "default";
477 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
481 uart1: serial@fdf00000 {
482 compatible = "arm,pl011", "arm,primecell";
483 reg = <0x0 0xfdf00000 0x0 0x1000>;
484 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
485 dma-names = "rx", "tx";
486 dmas = <&dma0 2 &dma0 3>;
487 clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
488 <&crg_ctrl HI3660_CLK_GATE_UART1>;
489 clock-names = "uartclk", "apb_pclk";
490 pinctrl-names = "default";
491 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
495 uart2: serial@fdf03000 {
496 compatible = "arm,pl011", "arm,primecell";
497 reg = <0x0 0xfdf03000 0x0 0x1000>;
498 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
499 dma-names = "rx", "tx";
500 dmas = <&dma0 4 &dma0 5>;
501 clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
502 <&crg_ctrl HI3660_PCLK>;
503 clock-names = "uartclk", "apb_pclk";
504 pinctrl-names = "default";
505 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
509 uart3: serial@ffd74000 {
510 compatible = "arm,pl011", "arm,primecell";
511 reg = <0x0 0xffd74000 0x0 0x1000>;
512 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
514 <&crg_ctrl HI3660_PCLK>;
515 clock-names = "uartclk", "apb_pclk";
516 pinctrl-names = "default";
517 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
521 uart4: serial@fdf01000 {
522 compatible = "arm,pl011", "arm,primecell";
523 reg = <0x0 0xfdf01000 0x0 0x1000>;
524 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
525 dma-names = "rx", "tx";
526 dmas = <&dma0 6 &dma0 7>;
527 clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
528 <&crg_ctrl HI3660_CLK_GATE_UART4>;
529 clock-names = "uartclk", "apb_pclk";
530 pinctrl-names = "default";
531 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
535 uart5: serial@fdf05000 {
536 compatible = "arm,pl011", "arm,primecell";
537 reg = <0x0 0xfdf05000 0x0 0x1000>;
538 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
539 dma-names = "rx", "tx";
540 dmas = <&dma0 8 &dma0 9>;
541 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
542 <&crg_ctrl HI3660_CLK_GATE_UART5>;
543 clock-names = "uartclk", "apb_pclk";
544 pinctrl-names = "default";
545 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
549 uart6: serial@fff32000 {
550 compatible = "arm,pl011", "arm,primecell";
551 reg = <0x0 0xfff32000 0x0 0x1000>;
552 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&crg_ctrl HI3660_CLK_UART6>,
554 <&crg_ctrl HI3660_PCLK>;
555 clock-names = "uartclk", "apb_pclk";
556 pinctrl-names = "default";
557 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
562 compatible = "hisilicon,k3-dma-1.0";
563 reg = <0x0 0xfdf30000 0x0 0x1000>;
567 dma-channel-mask = <0xfffe>;
568 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
571 dma-type = "hi3660_dma";
574 asp_dmac: dma-controller@e804b000 {
575 compatible = "hisilicon,hisi-pcm-asp-dma-1.0";
576 reg = <0x0 0xe804b000 0x0 0x1000>;
580 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
581 interrupt-names = "asp_dma_irq";
585 compatible = "arm,pl031", "arm,primecell";
586 reg = <0x0 0Xfff04000 0x0 0x1000>;
587 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&crg_ctrl HI3660_PCLK>;
589 clock-names = "apb_pclk";
592 gpio0: gpio@e8a0b000 {
593 compatible = "arm,pl061", "arm,primecell";
594 reg = <0 0xe8a0b000 0 0x1000>;
595 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
598 gpio-ranges = <&pmx0 1 0 7>;
599 interrupt-controller;
600 #interrupt-cells = <2>;
601 clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
602 clock-names = "apb_pclk";
605 gpio1: gpio@e8a0c000 {
606 compatible = "arm,pl061", "arm,primecell";
607 reg = <0 0xe8a0c000 0 0x1000>;
608 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
611 gpio-ranges = <&pmx0 1 7 7>;
612 interrupt-controller;
613 #interrupt-cells = <2>;
614 clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
615 clock-names = "apb_pclk";
618 gpio2: gpio@e8a0d000 {
619 compatible = "arm,pl061", "arm,primecell";
620 reg = <0 0xe8a0d000 0 0x1000>;
621 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
624 gpio-ranges = <&pmx0 0 14 8>;
625 interrupt-controller;
626 #interrupt-cells = <2>;
627 clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
628 clock-names = "apb_pclk";
631 gpio3: gpio@e8a0e000 {
632 compatible = "arm,pl061", "arm,primecell";
633 reg = <0 0xe8a0e000 0 0x1000>;
634 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
637 gpio-ranges = <&pmx0 0 22 8>;
638 interrupt-controller;
639 #interrupt-cells = <2>;
640 clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
641 clock-names = "apb_pclk";
644 gpio4: gpio@e8a0f000 {
645 compatible = "arm,pl061", "arm,primecell";
646 reg = <0 0xe8a0f000 0 0x1000>;
647 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
650 gpio-ranges = <&pmx0 0 30 8>;
651 interrupt-controller;
652 #interrupt-cells = <2>;
653 clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
654 clock-names = "apb_pclk";
657 gpio5: gpio@e8a10000 {
658 compatible = "arm,pl061", "arm,primecell";
659 reg = <0 0xe8a10000 0 0x1000>;
660 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
663 gpio-ranges = <&pmx0 0 38 8>;
664 interrupt-controller;
665 #interrupt-cells = <2>;
666 clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
667 clock-names = "apb_pclk";
670 gpio6: gpio@e8a11000 {
671 compatible = "arm,pl061", "arm,primecell";
672 reg = <0 0xe8a11000 0 0x1000>;
673 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
676 gpio-ranges = <&pmx0 0 46 8>;
677 interrupt-controller;
678 #interrupt-cells = <2>;
679 clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
680 clock-names = "apb_pclk";
683 gpio7: gpio@e8a12000 {
684 compatible = "arm,pl061", "arm,primecell";
685 reg = <0 0xe8a12000 0 0x1000>;
686 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
689 gpio-ranges = <&pmx0 0 54 8>;
690 interrupt-controller;
691 #interrupt-cells = <2>;
692 clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
693 clock-names = "apb_pclk";
696 gpio8: gpio@e8a13000 {
697 compatible = "arm,pl061", "arm,primecell";
698 reg = <0 0xe8a13000 0 0x1000>;
699 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
702 gpio-ranges = <&pmx0 0 62 8>;
703 interrupt-controller;
704 #interrupt-cells = <2>;
705 clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
706 clock-names = "apb_pclk";
709 gpio9: gpio@e8a14000 {
710 compatible = "arm,pl061", "arm,primecell";
711 reg = <0 0xe8a14000 0 0x1000>;
712 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
715 gpio-ranges = <&pmx0 0 70 8>;
716 interrupt-controller;
717 #interrupt-cells = <2>;
718 clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
719 clock-names = "apb_pclk";
722 gpio10: gpio@e8a15000 {
723 compatible = "arm,pl061", "arm,primecell";
724 reg = <0 0xe8a15000 0 0x1000>;
725 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
728 gpio-ranges = <&pmx0 0 78 8>;
729 interrupt-controller;
730 #interrupt-cells = <2>;
731 clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
732 clock-names = "apb_pclk";
735 gpio11: gpio@e8a16000 {
736 compatible = "arm,pl061", "arm,primecell";
737 reg = <0 0xe8a16000 0 0x1000>;
738 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
741 gpio-ranges = <&pmx0 0 86 8>;
742 interrupt-controller;
743 #interrupt-cells = <2>;
744 clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
745 clock-names = "apb_pclk";
748 gpio12: gpio@e8a17000 {
749 compatible = "arm,pl061", "arm,primecell";
750 reg = <0 0xe8a17000 0 0x1000>;
751 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
754 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
755 interrupt-controller;
756 #interrupt-cells = <2>;
757 clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
758 clock-names = "apb_pclk";
761 gpio13: gpio@e8a18000 {
762 compatible = "arm,pl061", "arm,primecell";
763 reg = <0 0xe8a18000 0 0x1000>;
764 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
767 gpio-ranges = <&pmx0 0 102 8>;
768 interrupt-controller;
769 #interrupt-cells = <2>;
770 clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
771 clock-names = "apb_pclk";
774 gpio14: gpio@e8a19000 {
775 compatible = "arm,pl061", "arm,primecell";
776 reg = <0 0xe8a19000 0 0x1000>;
777 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
780 gpio-ranges = <&pmx0 0 110 8>;
781 interrupt-controller;
782 #interrupt-cells = <2>;
783 clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
784 clock-names = "apb_pclk";
787 gpio15: gpio@e8a1a000 {
788 compatible = "arm,pl061", "arm,primecell";
789 reg = <0 0xe8a1a000 0 0x1000>;
790 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
793 gpio-ranges = <&pmx0 0 118 6>;
794 interrupt-controller;
795 #interrupt-cells = <2>;
796 clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
797 clock-names = "apb_pclk";
800 gpio16: gpio@e8a1b000 {
801 compatible = "arm,pl061", "arm,primecell";
802 reg = <0 0xe8a1b000 0 0x1000>;
803 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
806 interrupt-controller;
807 #interrupt-cells = <2>;
808 clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
809 clock-names = "apb_pclk";
812 gpio17: gpio@e8a1c000 {
813 compatible = "arm,pl061", "arm,primecell";
814 reg = <0 0xe8a1c000 0 0x1000>;
815 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
818 interrupt-controller;
819 #interrupt-cells = <2>;
820 clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
821 clock-names = "apb_pclk";
824 gpio18: gpio@ff3b4000 {
825 compatible = "arm,pl061", "arm,primecell";
826 reg = <0 0xff3b4000 0 0x1000>;
827 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
830 gpio-ranges = <&pmx2 0 0 8>;
831 interrupt-controller;
832 #interrupt-cells = <2>;
833 clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
834 clock-names = "apb_pclk";
837 gpio19: gpio@ff3b5000 {
838 compatible = "arm,pl061", "arm,primecell";
839 reg = <0 0xff3b5000 0 0x1000>;
840 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
843 gpio-ranges = <&pmx2 0 8 4>;
844 interrupt-controller;
845 #interrupt-cells = <2>;
846 clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
847 clock-names = "apb_pclk";
850 gpio20: gpio@e8a1f000 {
851 compatible = "arm,pl061", "arm,primecell";
852 reg = <0 0xe8a1f000 0 0x1000>;
853 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
856 gpio-ranges = <&pmx1 0 0 6>;
857 interrupt-controller;
858 #interrupt-cells = <2>;
859 clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
860 clock-names = "apb_pclk";
863 gpio21: gpio@e8a20000 {
864 compatible = "arm,pl061", "arm,primecell";
865 reg = <0 0xe8a20000 0 0x1000>;
866 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
869 interrupt-controller;
870 #interrupt-cells = <2>;
871 gpio-ranges = <&pmx3 0 0 6>;
872 clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
873 clock-names = "apb_pclk";
876 gpio22: gpio@fff0b000 {
877 compatible = "arm,pl061", "arm,primecell";
878 reg = <0 0xfff0b000 0 0x1000>;
879 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
883 gpio-ranges = <&pmx4 2 0 6>;
884 interrupt-controller;
885 #interrupt-cells = <2>;
886 clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
887 clock-names = "apb_pclk";
890 gpio23: gpio@fff0c000 {
891 compatible = "arm,pl061", "arm,primecell";
892 reg = <0 0xfff0c000 0 0x1000>;
893 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
897 gpio-ranges = <&pmx4 0 6 7>;
898 interrupt-controller;
899 #interrupt-cells = <2>;
900 clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
901 clock-names = "apb_pclk";
904 gpio24: gpio@fff0d000 {
905 compatible = "arm,pl061", "arm,primecell";
906 reg = <0 0xfff0d000 0 0x1000>;
907 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
911 gpio-ranges = <&pmx4 0 13 8>;
912 interrupt-controller;
913 #interrupt-cells = <2>;
914 clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
915 clock-names = "apb_pclk";
918 gpio25: gpio@fff0e000 {
919 compatible = "arm,pl061", "arm,primecell";
920 reg = <0 0xfff0e000 0 0x1000>;
921 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
925 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
926 interrupt-controller;
927 #interrupt-cells = <2>;
928 clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
929 clock-names = "apb_pclk";
932 gpio26: gpio@fff0f000 {
933 compatible = "arm,pl061", "arm,primecell";
934 reg = <0 0xfff0f000 0 0x1000>;
935 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
939 gpio-ranges = <&pmx4 0 28 8>;
940 interrupt-controller;
941 #interrupt-cells = <2>;
942 clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
943 clock-names = "apb_pclk";
946 gpio27: gpio@fff10000 {
947 compatible = "arm,pl061", "arm,primecell";
948 reg = <0 0xfff10000 0 0x1000>;
949 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
953 gpio-ranges = <&pmx4 0 36 6>;
954 interrupt-controller;
955 #interrupt-cells = <2>;
956 clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
957 clock-names = "apb_pclk";
960 gpio28: gpio@fff1d000 {
961 compatible = "arm,pl061", "arm,primecell";
962 reg = <0 0xfff1d000 0 0x1000>;
963 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
966 interrupt-controller;
967 #interrupt-cells = <2>;
968 clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
969 clock-names = "apb_pclk";
973 compatible = "arm,pl022", "arm,primecell";
974 reg = <0x0 0xffd68000 0x0 0x1000>;
975 #address-cells = <1>;
977 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>, <&crg_ctrl HI3660_CLK_GATE_SPI2>;
979 clock-names = "sspclk", "apb_pclk";
980 pinctrl-names = "default";
981 pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>;
983 cs-gpios = <&gpio27 2 0>;
988 compatible = "arm,pl022", "arm,primecell";
989 reg = <0x0 0xff3b3000 0x0 0x1000>;
990 #address-cells = <1>;
992 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
993 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>, <&crg_ctrl HI3660_CLK_GATE_SPI3>;
994 clock-names = "sspclk", "apb_pclk";
995 pinctrl-names = "default";
996 pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>;
998 cs-gpios = <&gpio18 5 0>;
1003 compatible = "hisilicon,kirin960-pcie";
1004 reg = <0x0 0xf4000000 0x0 0x1000>,
1005 <0x0 0xff3fe000 0x0 0x1000>,
1006 <0x0 0xf3f20000 0x0 0x40000>,
1007 <0x0 0xf5000000 0x0 0x2000>;
1008 reg-names = "dbi", "apb", "phy", "config";
1009 bus-range = <0x0 0xff>;
1010 #address-cells = <3>;
1012 device_type = "pci";
1013 ranges = <0x02000000 0x0 0x00000000
1017 #interrupt-cells = <1>;
1018 interrupts = <0 283 4>;
1019 interrupt-names = "msi";
1020 interrupt-map-mask = <0xf800 0 0 7>;
1021 interrupt-map = <0x0 0 0 1
1022 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1024 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1026 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1028 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
1029 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
1030 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
1031 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
1032 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
1033 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
1034 clock-names = "pcie_phy_ref", "pcie_aux",
1035 "pcie_apb_phy", "pcie_apb_sys",
1037 reset-gpios = <&gpio11 1 0 >;
1042 compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
1043 /* 0: HCI standard */
1044 /* 1: UFS SYS CTRL */
1045 reg = <0x0 0xff3b0000 0x0 0x1000>,
1046 <0x0 0xff3b1000 0x0 0x1000>;
1047 interrupt-parent = <&gic>;
1048 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
1050 <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
1051 clock-names = "ref_clk", "phy_clk";
1052 freq-table-hz = <0 0>,
1054 /* offset: 0x84; bit: 12 */
1055 resets = <&crg_rst 0x84 12>;
1056 reset-names = "rst";
1060 dwmmc1: dwmmc1@ff37f000 {
1061 compatible = "hisilicon,hi3660-dw-mshc";
1062 reg = <0x0 0xff37f000 0x0 0x1000>;
1063 #address-cells = <1>;
1065 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1066 clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
1067 <&crg_ctrl HI3660_HCLK_GATE_SD>;
1068 clock-names = "ciu", "biu";
1069 clock-frequency = <3200000>;
1070 resets = <&crg_rst 0x94 18>;
1071 reset-names = "reset";
1072 hisilicon,peripheral-syscon = <&sctrl>;
1073 card-detect-delay = <200>;
1074 status = "disabled";
1078 dwmmc2: dwmmc2@ff3ff000 {
1079 compatible = "hisilicon,hi3660-dw-mshc";
1080 reg = <0x0 0xff3ff000 0x0 0x1000>;
1081 #address-cells = <0x1>;
1082 #size-cells = <0x0>;
1083 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1084 clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
1085 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
1086 clock-names = "ciu", "biu";
1087 resets = <&crg_rst 0x94 20>;
1088 reset-names = "reset";
1089 card-detect-delay = <200>;
1090 status = "disabled";
1093 watchdog0: watchdog@e8a06000 {
1094 compatible = "arm,sp805", "arm,primecell";
1095 reg = <0x0 0xe8a06000 0x0 0x1000>;
1096 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1097 clocks = <&crg_ctrl HI3660_OSC32K>,
1098 <&crg_ctrl HI3660_OSC32K>;
1099 clock-names = "wdog_clk", "apb_pclk";
1102 watchdog1: watchdog@e8a07000 {
1103 compatible = "arm,sp805", "arm,primecell";
1104 reg = <0x0 0xe8a07000 0x0 0x1000>;
1105 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1106 clocks = <&crg_ctrl HI3660_OSC32K>,
1107 <&crg_ctrl HI3660_OSC32K>;
1108 clock-names = "wdog_clk", "apb_pclk";
1111 tsensor: tsensor@fff30000 {
1112 compatible = "hisilicon,hi3660-tsensor";
1113 reg = <0x0 0xfff30000 0x0 0x1000>;
1114 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1115 #thermal-sensor-cells = <1>;
1120 cls0: cls0-thermal {
1121 polling-delay = <1000>;
1122 polling-delay-passive = <100>;
1123 sustainable-power = <4500>;
1126 thermal-sensors = <&tsensor 1>;
1129 threshold: trip-point0 {
1130 temperature = <65000>;
1131 hysteresis = <1000>;
1135 target: trip-point1 {
1136 temperature = <75000>;
1137 hysteresis = <1000>;
1145 contribution = <1024>;
1146 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1147 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1148 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1149 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1153 contribution = <512>;
1154 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1155 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1156 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1157 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1163 usb3_otg_bc: usb3_otg_bc@ff200000 {
1164 compatible = "syscon", "simple-mfd";
1165 reg = <0x0 0xff200000 0x0 0x1000>;
1168 compatible = "hisilicon,hi3660-usb-phy";
1170 hisilicon,pericrg-syscon = <&crg_ctrl>;
1171 hisilicon,pctrl-syscon = <&pctrl>;
1172 hisilicon,eye-diagram-param = <0x22466e4>;
1176 dwc3: usb@ff100000 {
1177 compatible = "snps,dwc3";
1178 reg = <0x0 0xff100000 0x0 0x100000>;
1180 clocks = <&crg_ctrl HI3660_CLK_ABB_USB>,
1181 <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
1182 clock-names = "ref", "bus_early";
1184 assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
1185 assigned-clock-rates = <229000000>;
1187 resets = <&crg_rst 0x90 8>,
1192 interrupts = <0 159 4>, <0 161 4>;
1194 phy-names = "usb3-phy";
1199 #include "hi3660-coresight.dtsi"