1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Hisilicon Hi3660 SoC
5 * Copyright (C) 2016, Hisilicon Ltd.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/hi3660-clock.h>
12 compatible = "hisilicon,hi3660";
13 interrupt-parent = <&gic>;
18 compatible = "arm,psci-0.2";
58 compatible = "arm,cortex-a53", "arm,armv8";
61 enable-method = "psci";
62 next-level-cache = <&A53_L2>;
63 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
67 compatible = "arm,cortex-a53", "arm,armv8";
70 enable-method = "psci";
71 next-level-cache = <&A53_L2>;
72 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
76 compatible = "arm,cortex-a53", "arm,armv8";
79 enable-method = "psci";
80 next-level-cache = <&A53_L2>;
81 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
85 compatible = "arm,cortex-a53", "arm,armv8";
88 enable-method = "psci";
89 next-level-cache = <&A53_L2>;
90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;
94 compatible = "arm,cortex-a73", "arm,armv8";
97 enable-method = "psci";
98 next-level-cache = <&A73_L2>;
107 compatible = "arm,cortex-a73", "arm,armv8";
110 enable-method = "psci";
111 next-level-cache = <&A73_L2>;
120 compatible = "arm,cortex-a73", "arm,armv8";
123 enable-method = "psci";
124 next-level-cache = <&A73_L2>;
133 compatible = "arm,cortex-a73", "arm,armv8";
136 enable-method = "psci";
137 next-level-cache = <&A73_L2>;
146 entry-method = "psci";
149 compatible = "arm,idle-state";
150 arm,psci-suspend-param = <0x0000001>;
151 entry-latency-us = <7>;
152 exit-latency-us = <2>;
153 min-residency-us = <15>;
156 CPU_SLEEP: cpu-sleep {
157 compatible = "arm,idle-state";
159 arm,psci-suspend-param = <0x0010000>;
160 entry-latency-us = <40>;
161 exit-latency-us = <70>;
162 min-residency-us = <3000>;
165 CLUSTER_SLEEP_0: cluster-sleep-0 {
166 compatible = "arm,idle-state";
168 arm,psci-suspend-param = <0x1010000>;
169 entry-latency-us = <500>;
170 exit-latency-us = <5000>;
171 min-residency-us = <20000>;
174 CLUSTER_SLEEP_1: cluster-sleep-1 {
175 compatible = "arm,idle-state";
177 arm,psci-suspend-param = <0x1010000>;
178 entry-latency-us = <1000>;
179 exit-latency-us = <5000>;
180 min-residency-us = <20000>;
185 compatible = "cache";
189 compatible = "cache";
193 gic: interrupt-controller@e82b0000 {
194 compatible = "arm,gic-400";
195 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
196 <0x0 0xe82b2000 0 0x2000>, /* GICC */
197 <0x0 0xe82b4000 0 0x2000>, /* GICH */
198 <0x0 0xe82b6000 0 0x2000>; /* GICV */
199 #address-cells = <0>;
200 #interrupt-cells = <3>;
201 interrupt-controller;
202 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
203 IRQ_TYPE_LEVEL_HIGH)>;
207 compatible = "arm,armv8-pmuv3";
208 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
216 interrupt-affinity = <&cpu0>,
227 compatible = "arm,armv8-timer";
228 interrupt-parent = <&gic>;
229 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
230 IRQ_TYPE_LEVEL_LOW)>,
231 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
232 IRQ_TYPE_LEVEL_LOW)>,
233 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
234 IRQ_TYPE_LEVEL_LOW)>,
235 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
236 IRQ_TYPE_LEVEL_LOW)>;
240 compatible = "simple-bus";
241 #address-cells = <2>;
245 crg_ctrl: crg_ctrl@fff35000 {
246 compatible = "hisilicon,hi3660-crgctrl", "syscon";
247 reg = <0x0 0xfff35000 0x0 0x1000>;
251 crg_rst: crg_rst_controller {
252 compatible = "hisilicon,hi3660-reset";
254 hisi,rst-syscon = <&crg_ctrl>;
258 pctrl: pctrl@e8a09000 {
259 compatible = "hisilicon,hi3660-pctrl", "syscon";
260 reg = <0x0 0xe8a09000 0x0 0x2000>;
264 pmuctrl: crg_ctrl@fff34000 {
265 compatible = "hisilicon,hi3660-pmuctrl", "syscon";
266 reg = <0x0 0xfff34000 0x0 0x1000>;
270 sctrl: sctrl@fff0a000 {
271 compatible = "hisilicon,hi3660-sctrl", "syscon";
272 reg = <0x0 0xfff0a000 0x0 0x1000>;
276 iomcu: iomcu@ffd7e000 {
277 compatible = "hisilicon,hi3660-iomcu", "syscon";
278 reg = <0x0 0xffd7e000 0x0 0x1000>;
284 compatible = "hisilicon,hi3660-reset";
285 hisi,rst-syscon = <&iomcu>;
289 dual_timer0: timer@fff14000 {
290 compatible = "arm,sp804", "arm,primecell";
291 reg = <0x0 0xfff14000 0x0 0x1000>;
292 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&crg_ctrl HI3660_OSC32K>,
295 <&crg_ctrl HI3660_OSC32K>,
296 <&crg_ctrl HI3660_OSC32K>;
297 clock-names = "timer1", "timer2", "apb_pclk";
301 compatible = "snps,designware-i2c";
302 reg = <0x0 0xffd71000 0x0 0x1000>;
303 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
304 #address-cells = <1>;
306 clock-frequency = <400000>;
307 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
308 resets = <&iomcu_rst 0x20 3>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
315 compatible = "snps,designware-i2c";
316 reg = <0x0 0xffd72000 0x0 0x1000>;
317 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
318 #address-cells = <1>;
320 clock-frequency = <400000>;
321 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
322 resets = <&iomcu_rst 0x20 4>;
323 pinctrl-names = "default";
324 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
329 compatible = "snps,designware-i2c";
330 reg = <0x0 0xfdf0c000 0x0 0x1000>;
331 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
332 #address-cells = <1>;
334 clock-frequency = <400000>;
335 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
336 resets = <&crg_rst 0x78 7>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
343 compatible = "snps,designware-i2c";
344 reg = <0x0 0xfdf0b000 0x0 0x1000>;
345 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
346 #address-cells = <1>;
348 clock-frequency = <400000>;
349 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
350 resets = <&crg_rst 0x60 14>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
356 uart0: serial@fdf02000 {
357 compatible = "arm,pl011", "arm,primecell";
358 reg = <0x0 0xfdf02000 0x0 0x1000>;
359 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
361 <&crg_ctrl HI3660_PCLK>;
362 clock-names = "uartclk", "apb_pclk";
363 pinctrl-names = "default";
364 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
368 uart1: serial@fdf00000 {
369 compatible = "arm,pl011", "arm,primecell";
370 reg = <0x0 0xfdf00000 0x0 0x1000>;
371 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
373 <&crg_ctrl HI3660_CLK_GATE_UART1>;
374 clock-names = "uartclk", "apb_pclk";
375 pinctrl-names = "default";
376 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
380 uart2: serial@fdf03000 {
381 compatible = "arm,pl011", "arm,primecell";
382 reg = <0x0 0xfdf03000 0x0 0x1000>;
383 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
385 <&crg_ctrl HI3660_PCLK>;
386 clock-names = "uartclk", "apb_pclk";
387 pinctrl-names = "default";
388 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
392 uart3: serial@ffd74000 {
393 compatible = "arm,pl011", "arm,primecell";
394 reg = <0x0 0xffd74000 0x0 0x1000>;
395 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
397 <&crg_ctrl HI3660_PCLK>;
398 clock-names = "uartclk", "apb_pclk";
399 pinctrl-names = "default";
400 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
404 uart4: serial@fdf01000 {
405 compatible = "arm,pl011", "arm,primecell";
406 reg = <0x0 0xfdf01000 0x0 0x1000>;
407 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
409 <&crg_ctrl HI3660_CLK_GATE_UART4>;
410 clock-names = "uartclk", "apb_pclk";
411 pinctrl-names = "default";
412 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
416 uart5: serial@fdf05000 {
417 compatible = "arm,pl011", "arm,primecell";
418 reg = <0x0 0xfdf05000 0x0 0x1000>;
419 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
421 <&crg_ctrl HI3660_CLK_GATE_UART5>;
422 clock-names = "uartclk", "apb_pclk";
423 pinctrl-names = "default";
424 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
428 uart6: serial@fff32000 {
429 compatible = "arm,pl011", "arm,primecell";
430 reg = <0x0 0xfff32000 0x0 0x1000>;
431 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&crg_ctrl HI3660_CLK_UART6>,
433 <&crg_ctrl HI3660_PCLK>;
434 clock-names = "uartclk", "apb_pclk";
435 pinctrl-names = "default";
436 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
441 compatible = "hisilicon,k3-dma-1.0";
442 reg = <0x0 0xfdf30000 0x0 0x1000>;
447 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
450 dma-type = "hi3660_dma";
454 compatible = "arm,pl031", "arm,primecell";
455 reg = <0x0 0Xfff04000 0x0 0x1000>;
456 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&crg_ctrl HI3660_PCLK>;
458 clock-names = "apb_pclk";
461 gpio0: gpio@e8a0b000 {
462 compatible = "arm,pl061", "arm,primecell";
463 reg = <0 0xe8a0b000 0 0x1000>;
464 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
467 gpio-ranges = <&pmx0 1 0 7>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
470 clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
471 clock-names = "apb_pclk";
474 gpio1: gpio@e8a0c000 {
475 compatible = "arm,pl061", "arm,primecell";
476 reg = <0 0xe8a0c000 0 0x1000>;
477 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
480 gpio-ranges = <&pmx0 1 7 7>;
481 interrupt-controller;
482 #interrupt-cells = <2>;
483 clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
484 clock-names = "apb_pclk";
487 gpio2: gpio@e8a0d000 {
488 compatible = "arm,pl061", "arm,primecell";
489 reg = <0 0xe8a0d000 0 0x1000>;
490 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
493 gpio-ranges = <&pmx0 0 14 8>;
494 interrupt-controller;
495 #interrupt-cells = <2>;
496 clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
497 clock-names = "apb_pclk";
500 gpio3: gpio@e8a0e000 {
501 compatible = "arm,pl061", "arm,primecell";
502 reg = <0 0xe8a0e000 0 0x1000>;
503 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
506 gpio-ranges = <&pmx0 0 22 8>;
507 interrupt-controller;
508 #interrupt-cells = <2>;
509 clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
510 clock-names = "apb_pclk";
513 gpio4: gpio@e8a0f000 {
514 compatible = "arm,pl061", "arm,primecell";
515 reg = <0 0xe8a0f000 0 0x1000>;
516 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
519 gpio-ranges = <&pmx0 0 30 8>;
520 interrupt-controller;
521 #interrupt-cells = <2>;
522 clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
523 clock-names = "apb_pclk";
526 gpio5: gpio@e8a10000 {
527 compatible = "arm,pl061", "arm,primecell";
528 reg = <0 0xe8a10000 0 0x1000>;
529 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
532 gpio-ranges = <&pmx0 0 38 8>;
533 interrupt-controller;
534 #interrupt-cells = <2>;
535 clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
536 clock-names = "apb_pclk";
539 gpio6: gpio@e8a11000 {
540 compatible = "arm,pl061", "arm,primecell";
541 reg = <0 0xe8a11000 0 0x1000>;
542 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
545 gpio-ranges = <&pmx0 0 46 8>;
546 interrupt-controller;
547 #interrupt-cells = <2>;
548 clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
549 clock-names = "apb_pclk";
552 gpio7: gpio@e8a12000 {
553 compatible = "arm,pl061", "arm,primecell";
554 reg = <0 0xe8a12000 0 0x1000>;
555 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
558 gpio-ranges = <&pmx0 0 54 8>;
559 interrupt-controller;
560 #interrupt-cells = <2>;
561 clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
562 clock-names = "apb_pclk";
565 gpio8: gpio@e8a13000 {
566 compatible = "arm,pl061", "arm,primecell";
567 reg = <0 0xe8a13000 0 0x1000>;
568 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
571 gpio-ranges = <&pmx0 0 62 8>;
572 interrupt-controller;
573 #interrupt-cells = <2>;
574 clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
575 clock-names = "apb_pclk";
578 gpio9: gpio@e8a14000 {
579 compatible = "arm,pl061", "arm,primecell";
580 reg = <0 0xe8a14000 0 0x1000>;
581 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
584 gpio-ranges = <&pmx0 0 70 8>;
585 interrupt-controller;
586 #interrupt-cells = <2>;
587 clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
588 clock-names = "apb_pclk";
591 gpio10: gpio@e8a15000 {
592 compatible = "arm,pl061", "arm,primecell";
593 reg = <0 0xe8a15000 0 0x1000>;
594 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
597 gpio-ranges = <&pmx0 0 78 8>;
598 interrupt-controller;
599 #interrupt-cells = <2>;
600 clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
601 clock-names = "apb_pclk";
604 gpio11: gpio@e8a16000 {
605 compatible = "arm,pl061", "arm,primecell";
606 reg = <0 0xe8a16000 0 0x1000>;
607 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
610 gpio-ranges = <&pmx0 0 86 8>;
611 interrupt-controller;
612 #interrupt-cells = <2>;
613 clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
614 clock-names = "apb_pclk";
617 gpio12: gpio@e8a17000 {
618 compatible = "arm,pl061", "arm,primecell";
619 reg = <0 0xe8a17000 0 0x1000>;
620 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
623 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
624 interrupt-controller;
625 #interrupt-cells = <2>;
626 clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
627 clock-names = "apb_pclk";
630 gpio13: gpio@e8a18000 {
631 compatible = "arm,pl061", "arm,primecell";
632 reg = <0 0xe8a18000 0 0x1000>;
633 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
636 gpio-ranges = <&pmx0 0 102 8>;
637 interrupt-controller;
638 #interrupt-cells = <2>;
639 clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
640 clock-names = "apb_pclk";
643 gpio14: gpio@e8a19000 {
644 compatible = "arm,pl061", "arm,primecell";
645 reg = <0 0xe8a19000 0 0x1000>;
646 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
649 gpio-ranges = <&pmx0 0 110 8>;
650 interrupt-controller;
651 #interrupt-cells = <2>;
652 clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
653 clock-names = "apb_pclk";
656 gpio15: gpio@e8a1a000 {
657 compatible = "arm,pl061", "arm,primecell";
658 reg = <0 0xe8a1a000 0 0x1000>;
659 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
662 gpio-ranges = <&pmx0 0 118 6>;
663 interrupt-controller;
664 #interrupt-cells = <2>;
665 clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
666 clock-names = "apb_pclk";
669 gpio16: gpio@e8a1b000 {
670 compatible = "arm,pl061", "arm,primecell";
671 reg = <0 0xe8a1b000 0 0x1000>;
672 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
675 interrupt-controller;
676 #interrupt-cells = <2>;
677 clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
678 clock-names = "apb_pclk";
681 gpio17: gpio@e8a1c000 {
682 compatible = "arm,pl061", "arm,primecell";
683 reg = <0 0xe8a1c000 0 0x1000>;
684 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
687 interrupt-controller;
688 #interrupt-cells = <2>;
689 clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
690 clock-names = "apb_pclk";
693 gpio18: gpio@ff3b4000 {
694 compatible = "arm,pl061", "arm,primecell";
695 reg = <0 0xff3b4000 0 0x1000>;
696 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
699 gpio-ranges = <&pmx2 0 0 8>;
700 interrupt-controller;
701 #interrupt-cells = <2>;
702 clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
703 clock-names = "apb_pclk";
706 gpio19: gpio@ff3b5000 {
707 compatible = "arm,pl061", "arm,primecell";
708 reg = <0 0xff3b5000 0 0x1000>;
709 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
712 gpio-ranges = <&pmx2 0 8 4>;
713 interrupt-controller;
714 #interrupt-cells = <2>;
715 clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
716 clock-names = "apb_pclk";
719 gpio20: gpio@e8a1f000 {
720 compatible = "arm,pl061", "arm,primecell";
721 reg = <0 0xe8a1f000 0 0x1000>;
722 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
725 gpio-ranges = <&pmx1 0 0 6>;
726 interrupt-controller;
727 #interrupt-cells = <2>;
728 clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
729 clock-names = "apb_pclk";
732 gpio21: gpio@e8a20000 {
733 compatible = "arm,pl061", "arm,primecell";
734 reg = <0 0xe8a20000 0 0x1000>;
735 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
738 interrupt-controller;
739 #interrupt-cells = <2>;
740 gpio-ranges = <&pmx3 0 0 6>;
741 clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
742 clock-names = "apb_pclk";
745 gpio22: gpio@fff0b000 {
746 compatible = "arm,pl061", "arm,primecell";
747 reg = <0 0xfff0b000 0 0x1000>;
748 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
752 gpio-ranges = <&pmx4 2 0 6>;
753 interrupt-controller;
754 #interrupt-cells = <2>;
755 clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
756 clock-names = "apb_pclk";
759 gpio23: gpio@fff0c000 {
760 compatible = "arm,pl061", "arm,primecell";
761 reg = <0 0xfff0c000 0 0x1000>;
762 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
766 gpio-ranges = <&pmx4 0 6 7>;
767 interrupt-controller;
768 #interrupt-cells = <2>;
769 clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
770 clock-names = "apb_pclk";
773 gpio24: gpio@fff0d000 {
774 compatible = "arm,pl061", "arm,primecell";
775 reg = <0 0xfff0d000 0 0x1000>;
776 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
780 gpio-ranges = <&pmx4 0 13 8>;
781 interrupt-controller;
782 #interrupt-cells = <2>;
783 clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
784 clock-names = "apb_pclk";
787 gpio25: gpio@fff0e000 {
788 compatible = "arm,pl061", "arm,primecell";
789 reg = <0 0xfff0e000 0 0x1000>;
790 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
794 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
795 interrupt-controller;
796 #interrupt-cells = <2>;
797 clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
798 clock-names = "apb_pclk";
801 gpio26: gpio@fff0f000 {
802 compatible = "arm,pl061", "arm,primecell";
803 reg = <0 0xfff0f000 0 0x1000>;
804 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
808 gpio-ranges = <&pmx4 0 28 8>;
809 interrupt-controller;
810 #interrupt-cells = <2>;
811 clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
812 clock-names = "apb_pclk";
815 gpio27: gpio@fff10000 {
816 compatible = "arm,pl061", "arm,primecell";
817 reg = <0 0xfff10000 0 0x1000>;
818 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
822 gpio-ranges = <&pmx4 0 36 6>;
823 interrupt-controller;
824 #interrupt-cells = <2>;
825 clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
826 clock-names = "apb_pclk";
829 gpio28: gpio@fff1d000 {
830 compatible = "arm,pl061", "arm,primecell";
831 reg = <0 0xfff1d000 0 0x1000>;
832 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-controller;
836 #interrupt-cells = <2>;
837 clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
838 clock-names = "apb_pclk";
842 compatible = "arm,pl022", "arm,primecell";
843 reg = <0x0 0xffd68000 0x0 0x1000>;
844 #address-cells = <1>;
846 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
848 clock-names = "apb_pclk";
849 pinctrl-names = "default";
850 pinctrl-0 = <&spi2_pmx_func>;
852 cs-gpios = <&gpio27 2 0>;
857 compatible = "arm,pl022", "arm,primecell";
858 reg = <0x0 0xff3b3000 0x0 0x1000>;
859 #address-cells = <1>;
861 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
863 clock-names = "apb_pclk";
864 pinctrl-names = "default";
865 pinctrl-0 = <&spi3_pmx_func>;
867 cs-gpios = <&gpio18 5 0>;
872 compatible = "hisilicon,kirin960-pcie";
873 reg = <0x0 0xf4000000 0x0 0x1000>,
874 <0x0 0xff3fe000 0x0 0x1000>,
875 <0x0 0xf3f20000 0x0 0x40000>,
876 <0x0 0xf5000000 0x0 0x2000>;
877 reg-names = "dbi", "apb", "phy", "config";
878 bus-range = <0x0 0x1>;
879 #address-cells = <3>;
882 ranges = <0x02000000 0x0 0x00000000
886 #interrupt-cells = <1>;
887 interrupt-map-mask = <0xf800 0 0 7>;
888 interrupt-map = <0x0 0 0 1
889 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
891 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
893 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
895 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
897 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
898 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
899 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
900 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
901 clock-names = "pcie_phy_ref", "pcie_aux",
902 "pcie_apb_phy", "pcie_apb_sys",
904 reset-gpios = <&gpio11 1 0 >;
908 dwmmc1: dwmmc1@ff37f000 {
909 #address-cells = <1>;
912 compatible = "hisilicon,hi3660-dw-mshc";
918 card-detect-delay = <200>;
919 reg = <0x0 0xff37f000 0x0 0x1000>;
920 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
922 <&crg_ctrl HI3660_HCLK_GATE_SD>;
923 clock-names = "ciu", "biu";
924 clock-frequency = <3200000>;
925 resets = <&crg_rst 0x94 18>;
926 reset-names = "reset";
927 cd-gpios = <&gpio25 3 0>;
928 hisilicon,peripheral-syscon = <&sctrl>;
929 pinctrl-names = "default";
930 pinctrl-0 = <&sd_pmx_func
947 dwmmc2: dwmmc2@ff3ff000 {
948 compatible = "hisilicon,hi3660-dw-mshc";
949 reg = <0x0 0xff3ff000 0x0 0x1000>;
950 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
952 clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
953 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
954 clock-names = "ciu", "biu";
955 resets = <&crg_rst 0x94 20>;
956 reset-names = "reset";
957 card-detect-delay = <200>;
959 keep-power-in-suspend;
960 pinctrl-names = "default";
961 pinctrl-0 = <&sdio_pmx_func
967 watchdog0: watchdog@e8a06000 {
968 compatible = "arm,sp805-wdt", "arm,primecell";
969 reg = <0x0 0xe8a06000 0x0 0x1000>;
970 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
971 clocks = <&crg_ctrl HI3660_OSC32K>;
972 clock-names = "apb_pclk";
975 watchdog1: watchdog@e8a07000 {
976 compatible = "arm,sp805-wdt", "arm,primecell";
977 reg = <0x0 0xe8a07000 0x0 0x1000>;
978 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
979 clocks = <&crg_ctrl HI3660_OSC32K>;
980 clock-names = "apb_pclk";