arch/arm64/boot/dts/freescale/tqmls1088a-mbls10xxa-mc.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
   2 /*
   3  * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
   4  * D-82229 Seefeld, Germany.
   5  * Author: Gregor Herburger, Timo Herbrecher
   6  *
   7  * Device Tree Include file for MBLS10xxA from TQ (MC related sections)
   8  */
   9
  10 #include <dt-bindings/net/ti-dp83867.h>
  11
  12 / {
  13         sfp1: sfp1 {
  14                 compatible = "sff,sfp";
  15                 i2c-bus = <&sfp1_i2c>;
  16                 mod-def0-gpios = <&gpioexp2 2 GPIO_ACTIVE_LOW>;
  17                 los-gpios = <&gpioexp2 3 GPIO_ACTIVE_HIGH>;
  18                 tx-fault-gpios = <&gpioexp2 0 GPIO_ACTIVE_HIGH>;
  19                 tx-disable-gpios = <&gpioexp2 1 GPIO_ACTIVE_HIGH>;
  20         };
  21
  22         sfp2: sfp2 {
  23                 compatible = "sff,sfp";
  24                 i2c-bus = <&sfp2_i2c>;
  25                 mod-def0-gpios = <&gpioexp2 10 GPIO_ACTIVE_LOW>;
  26                 los-gpios = <&gpioexp2 11 GPIO_ACTIVE_HIGH>;
  27                 tx-fault-gpios = <&gpioexp2 8 GPIO_ACTIVE_HIGH>;
  28                 tx-disable-gpios = <&gpioexp2 9 GPIO_ACTIVE_HIGH>;
  29         };
  30 };
  31
  32 &dpmac1 {
  33         pcs-handle = <&pcs1>;
  34 };
  35
  36 &dpmac2 {
  37         pcs-handle = <&pcs2>;
  38 };
  39
  40 &dpmac3 {
  41         pcs-handle = <&pcs3_0>;
  42 };
  43
  44 &dpmac4 {
  45         pcs-handle = <&pcs3_1>;
  46 };
  47
  48 &dpmac5 {
  49         pcs-handle = <&pcs3_2>;
  50 };
  51
  52 &dpmac6 {
  53         pcs-handle = <&pcs3_3>;
  54 };
  55
  56 &dpmac7 {
  57         pcs-handle = <&pcs7_0>;
  58 };
  59
  60 &dpmac8 {
  61         pcs-handle = <&pcs7_1>;
  62 };
  63
  64 &dpmac9 {
  65         pcs-handle = <&pcs7_2>;
  66 };
  67
  68 &dpmac10 {
  69         pcs-handle = <&pcs7_3>;
  70 };
  71
  72 &emdio1 {
  73         status = "okay";
  74
  75         qsgmii2_phy1: ethernet-phy@0 {
  76                 compatible = "ethernet-phy-ieee802.3-c22";
  77                 reg = <0x00>;
  78         };
  79
  80         qsgmii2_phy2: ethernet-phy@1 {
  81                 compatible = "ethernet-phy-ieee802.3-c22";
  82                 reg = <0x01>;
  83         };
  84
  85         qsgmii2_phy3: ethernet-phy@2 {
  86                 compatible = "ethernet-phy-ieee802.3-c22";
  87                 reg = <0x02>;
  88         };
  89
  90         qsgmii2_phy4: ethernet-phy@3 {
  91                 compatible = "ethernet-phy-ieee802.3-c22";
  92                 reg = <0x03>;
  93         };
  94
  95         rgmii_phy2: ethernet-phy@c {
  96                 compatible = "ethernet-phy-ieee802.3-c22";
  97                 reg = <0x0c>;
  98                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
  99                 ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
 100                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
 101         };
 102
 103         rgmii_phy1: ethernet-phy@e {
 104                 compatible = "ethernet-phy-ieee802.3-c22";
 105                 reg = <0x0e>;
 106                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
 107                 ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
 108                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
 109         };
 110
 111         qsgmii1_phy1: ethernet-phy@1c {
 112                 compatible = "ethernet-phy-ieee802.3-c22";
 113                 reg = <0x1c>;
 114         };
 115
 116         qsgmii1_phy2: ethernet-phy@1d {
 117                 compatible = "ethernet-phy-ieee802.3-c22";
 118                 reg = <0x1d>;
 119         };
 120
 121         qsgmii1_phy3: ethernet-phy@1e {
 122                 compatible = "ethernet-phy-ieee802.3-c22";
 123                 reg = <0x1e>;
 124         };
 125
 126         qsgmii1_phy4: ethernet-phy@1f {
 127                 compatible = "ethernet-phy-ieee802.3-c22";
 128                 reg = <0x1f>;
 129         };
 130 };
 131
 132 &pcs_mdio1 {
 133         status = "okay";
 134 };
 135
 136 &pcs_mdio2 {
 137         status = "okay";
 138 };
 139
 140 &pcs_mdio3 {
 141         status = "okay";
 142 };
 143
 144 &pcs_mdio7 {
 145         status = "okay";
 146 };