1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 * Copyright (c) 2021 SUSE LLC
6 * Copyright (c) 2017-2021 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "nxp,s32g2";
13 interrupt-parent = <&gic>;
23 compatible = "arm,cortex-a53";
25 enable-method = "psci";
26 next-level-cache = <&cluster0_l2>;
31 compatible = "arm,cortex-a53";
33 enable-method = "psci";
34 next-level-cache = <&cluster0_l2>;
39 compatible = "arm,cortex-a53";
41 enable-method = "psci";
42 next-level-cache = <&cluster1_l2>;
47 compatible = "arm,cortex-a53";
49 enable-method = "psci";
50 next-level-cache = <&cluster1_l2>;
53 cluster0_l2: l2-cache0 {
59 cluster1_l2: l2-cache1 {
67 compatible = "arm,cortex-a53-pmu";
68 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
72 compatible = "arm,armv8-timer";
73 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
74 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
75 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
76 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
81 compatible = "arm,psci-1.0";
87 compatible = "simple-bus";
90 ranges = <0 0 0 0x80000000>;
92 uart0: serial@401c8000 {
93 compatible = "nxp,s32g2-linflexuart",
94 "fsl,s32v234-linflexuart";
95 reg = <0x401c8000 0x3000>;
96 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
100 uart1: serial@401cc000 {
101 compatible = "nxp,s32g2-linflexuart",
102 "fsl,s32v234-linflexuart";
103 reg = <0x401cc000 0x3000>;
104 interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
108 uart2: serial@402bc000 {
109 compatible = "nxp,s32g2-linflexuart",
110 "fsl,s32v234-linflexuart";
111 reg = <0x402bc000 0x3000>;
112 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
116 gic: interrupt-controller@50800000 {
117 compatible = "arm,gic-v3";
118 reg = <0x50800000 0x10000>,
119 <0x50880000 0x80000>,
123 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
124 interrupt-controller;
125 #interrupt-cells = <3>;