1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 * Copyright (c) 2021 SUSE LLC
6 * Copyright (c) 2017-2021 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "nxp,s32g2";
13 interrupt-parent = <&gic>;
23 compatible = "arm,cortex-a53";
25 enable-method = "psci";
26 next-level-cache = <&cluster0_l2>;
31 compatible = "arm,cortex-a53";
33 enable-method = "psci";
34 next-level-cache = <&cluster0_l2>;
39 compatible = "arm,cortex-a53";
41 enable-method = "psci";
42 next-level-cache = <&cluster1_l2>;
47 compatible = "arm,cortex-a53";
49 enable-method = "psci";
50 next-level-cache = <&cluster1_l2>;
53 cluster0_l2: l2-cache0 {
57 cluster1_l2: l2-cache1 {
63 compatible = "arm,cortex-a53-pmu";
64 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
68 compatible = "arm,armv8-timer";
69 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
70 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
71 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
72 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
77 compatible = "arm,psci-1.0";
83 compatible = "simple-bus";
86 ranges = <0 0 0 0x80000000>;
88 uart0: serial@401c8000 {
89 compatible = "nxp,s32g2-linflexuart",
90 "fsl,s32v234-linflexuart";
91 reg = <0x401c8000 0x3000>;
92 interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
96 uart1: serial@401cc000 {
97 compatible = "nxp,s32g2-linflexuart",
98 "fsl,s32v234-linflexuart";
99 reg = <0x401cc000 0x3000>;
100 interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
104 uart2: serial@402bc000 {
105 compatible = "nxp,s32g2-linflexuart",
106 "fsl,s32v234-linflexuart";
107 reg = <0x402bc000 0x3000>;
108 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
112 gic: interrupt-controller@50800000 {
113 compatible = "arm,gic-v3";
114 reg = <0x50800000 0x10000>,
115 <0x50880000 0x80000>,
119 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
120 interrupt-controller;
121 #interrupt-cells = <3>;