arch/arm64/boot/dts/freescale/imx93.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2022 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx93-clock.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/power/fsl,imx93-power.h>
  11
  12 #include "imx93-pinfunc.h"
  13
  14 / {
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 i2c0 = &lpi2c1;
  21                 i2c1 = &lpi2c2;
  22                 i2c2 = &lpi2c3;
  23                 i2c3 = &lpi2c4;
  24                 i2c4 = &lpi2c5;
  25                 i2c5 = &lpi2c6;
  26                 i2c6 = &lpi2c7;
  27                 i2c7 = &lpi2c8;
  28                 mmc0 = &usdhc1;
  29                 mmc1 = &usdhc2;
  30                 mmc2 = &usdhc3;
  31                 serial0 = &lpuart1;
  32                 serial1 = &lpuart2;
  33                 serial2 = &lpuart3;
  34                 serial3 = &lpuart4;
  35                 serial4 = &lpuart5;
  36                 serial5 = &lpuart6;
  37                 serial6 = &lpuart7;
  38                 serial7 = &lpuart8;
  39         };
  40
  41         cpus {
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44
  45                 A55_0: cpu@0 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a55";
  48                         reg = <0x0>;
  49                         enable-method = "psci";
  50                         #cooling-cells = <2>;
  51                 };
  52
  53                 A55_1: cpu@100 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a55";
  56                         reg = <0x100>;
  57                         enable-method = "psci";
  58                         #cooling-cells = <2>;
  59                 };
  60
  61         };
  62
  63         osc_32k: clock-osc-32k {
  64                 compatible = "fixed-clock";
  65                 #clock-cells = <0>;
  66                 clock-frequency = <32768>;
  67                 clock-output-names = "osc_32k";
  68         };
  69
  70         osc_24m: clock-osc-24m {
  71                 compatible = "fixed-clock";
  72                 #clock-cells = <0>;
  73                 clock-frequency = <24000000>;
  74                 clock-output-names = "osc_24m";
  75         };
  76
  77         clk_ext1: clock-ext1 {
  78                 compatible = "fixed-clock";
  79                 #clock-cells = <0>;
  80                 clock-frequency = <133000000>;
  81                 clock-output-names = "clk_ext1";
  82         };
  83
  84         pmu {
  85                 compatible = "arm,cortex-a55-pmu";
  86                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  87         };
  88
  89         psci {
  90                 compatible = "arm,psci-1.0";
  91                 method = "smc";
  92         };
  93
  94         timer {
  95                 compatible = "arm,armv8-timer";
  96                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
  97                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
  98                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
  99                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
 100                 clock-frequency = <24000000>;
 101                 arm,no-tick-in-suspend;
 102                 interrupt-parent = <&gic>;
 103         };
 104
 105         gic: interrupt-controller@48000000 {
 106                 compatible = "arm,gic-v3";
 107                 reg = <0 0x48000000 0 0x10000>,
 108                       <0 0x48040000 0 0xc0000>;
 109                 #interrupt-cells = <3>;
 110                 interrupt-controller;
 111                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 112                 interrupt-parent = <&gic>;
 113         };
 114
 115         soc@0 {
 116                 compatible = "simple-bus";
 117                 #address-cells = <1>;
 118                 #size-cells = <1>;
 119                 ranges = <0x0 0x0 0x0 0x80000000>,
 120                          <0x28000000 0x0 0x28000000 0x10000000>;
 121
 122                 aips1: bus@44000000 {
 123                         compatible = "fsl,aips-bus", "simple-bus";
 124                         reg = <0x44000000 0x800000>;
 125                         #address-cells = <1>;
 126                         #size-cells = <1>;
 127                         ranges;
 128
 129                         anomix_ns_gpr: syscon@44210000 {
 130                                 compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon";
 131                                 reg = <0x44210000 0x1000>;
 132                         };
 133
 134                         mu1: mailbox@44230000 {
 135                                 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
 136                                 reg = <0x44230000 0x10000>;
 137                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 138                                 #mbox-cells = <2>;
 139                                 status = "disabled";
 140                         };
 141
 142                         system_counter: timer@44290000 {
 143                                 compatible = "nxp,sysctr-timer";
 144                                 reg = <0x44290000 0x30000>;
 145                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 146                                 clocks = <&osc_24m>;
 147                                 clock-names = "per";
 148                         };
 149
 150                         lpi2c1: i2c@44340000 {
 151                                 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 152                                 reg = <0x44340000 0x10000>;
 153                                 #address-cells = <1>;
 154                                 #size-cells = <0>;
 155                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 156                                 clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
 157                                          <&clk IMX93_CLK_BUS_AON>;
 158                                 clock-names = "per", "ipg";
 159                                 status = "disabled";
 160                         };
 161
 162                         lpi2c2: i2c@44350000 {
 163                                 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 164                                 reg = <0x44350000 0x10000>;
 165                                 #address-cells = <1>;
 166                                 #size-cells = <0>;
 167                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 168                                 clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
 169                                          <&clk IMX93_CLK_BUS_AON>;
 170                                 clock-names = "per", "ipg";
 171                                 status = "disabled";
 172                         };
 173
 174                         lpspi1: spi@44360000 {
 175                                 #address-cells = <1>;
 176                                 #size-cells = <0>;
 177                                 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
 178                                 reg = <0x44360000 0x10000>;
 179                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 180                                 clocks = <&clk IMX93_CLK_LPSPI1_GATE>,
 181                                          <&clk IMX93_CLK_BUS_AON>;
 182                                 clock-names = "per", "ipg";
 183                                 status = "disabled";
 184                         };
 185
 186                         lpspi2: spi@44370000 {
 187                                 #address-cells = <1>;
 188                                 #size-cells = <0>;
 189                                 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
 190                                 reg = <0x44370000 0x10000>;
 191                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 192                                 clocks = <&clk IMX93_CLK_LPSPI2_GATE>,
 193                                          <&clk IMX93_CLK_BUS_AON>;
 194                                 clock-names = "per", "ipg";
 195                                 status = "disabled";
 196                         };
 197
 198                         lpuart1: serial@44380000 {
 199                                 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
 200                                 reg = <0x44380000 0x1000>;
 201                                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 202                                 clocks = <&clk IMX93_CLK_LPUART1_GATE>;
 203                                 clock-names = "ipg";
 204                                 status = "disabled";
 205                         };
 206
 207                         lpuart2: serial@44390000 {
 208                                 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
 209                                 reg = <0x44390000 0x1000>;
 210                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 211                                 clocks = <&clk IMX93_CLK_LPUART2_GATE>;
 212                                 clock-names = "ipg";
 213                                 status = "disabled";
 214                         };
 215
 216                         iomuxc: pinctrl@443c0000 {
 217                                 compatible = "fsl,imx93-iomuxc";
 218                                 reg = <0x443c0000 0x10000>;
 219                                 status = "okay";
 220                         };
 221
 222                         clk: clock-controller@44450000 {
 223                                 compatible = "fsl,imx93-ccm";
 224                                 reg = <0x44450000 0x10000>;
 225                                 #clock-cells = <1>;
 226                                 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
 227                                 clock-names = "osc_32k", "osc_24m", "clk_ext1";
 228                                 status = "okay";
 229                         };
 230
 231                         src: system-controller@44460000 {
 232                                 compatible = "fsl,imx93-src", "syscon";
 233                                 reg = <0x44460000 0x10000>;
 234                                 #address-cells = <1>;
 235                                 #size-cells = <1>;
 236                                 ranges;
 237
 238                                 mediamix: power-domain@44462400 {
 239                                         compatible = "fsl,imx93-src-slice";
 240                                         reg = <0x44462400 0x400>, <0x44465800 0x400>;
 241                                         #power-domain-cells = <0>;
 242                                         clocks = <&clk IMX93_CLK_MEDIA_AXI>,
 243                                                  <&clk IMX93_CLK_MEDIA_APB>;
 244                                 };
 245
 246                                 mlmix: power-domain@44461800 {
 247                                         compatible = "fsl,imx93-src-slice";
 248                                         reg = <0x44461800 0x400>, <0x44464800 0x400>;
 249                                         #power-domain-cells = <0>;
 250                                         clocks = <&clk IMX93_CLK_ML_APB>,
 251                                                  <&clk IMX93_CLK_ML>;
 252                                 };
 253                         };
 254
 255                         anatop: anatop@44480000 {
 256                                 compatible = "fsl,imx93-anatop", "syscon";
 257                                 reg = <0x44480000 0x2000>;
 258                         };
 259                 };
 260
 261                 aips2: bus@42000000 {
 262                         compatible = "fsl,aips-bus", "simple-bus";
 263                         reg = <0x42000000 0x800000>;
 264                         #address-cells = <1>;
 265                         #size-cells = <1>;
 266                         ranges;
 267
 268                         wakeupmix_gpr: syscon@42420000 {
 269                                 compatible = "fsl,imx93-wakeupmix-syscfg", "syscon";
 270                                 reg = <0x42420000 0x1000>;
 271                         };
 272
 273                         mu2: mailbox@42440000 {
 274                                 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
 275                                 reg = <0x42440000 0x10000>;
 276                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 277                                 #mbox-cells = <2>;
 278                                 status = "disabled";
 279                         };
 280
 281                         lpi2c3: i2c@42530000 {
 282                                 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 283                                 reg = <0x42530000 0x10000>;
 284                                 #address-cells = <1>;
 285                                 #size-cells = <0>;
 286                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 287                                 clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
 288                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 289                                 clock-names = "per", "ipg";
 290                                 status = "disabled";
 291                         };
 292
 293                         lpi2c4: i2c@42540000 {
 294                                 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 295                                 reg = <0x42540000 0x10000>;
 296                                 #address-cells = <1>;
 297                                 #size-cells = <0>;
 298                                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 299                                 clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
 300                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 301                                 clock-names = "per", "ipg";
 302                                 status = "disabled";
 303                         };
 304
 305                         lpuart3: serial@42570000 {
 306                                 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
 307                                 reg = <0x42570000 0x1000>;
 308                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 309                                 clocks = <&clk IMX93_CLK_LPUART3_GATE>;
 310                                 clock-names = "ipg";
 311                                 status = "disabled";
 312                         };
 313
 314                         lpuart4: serial@42580000 {
 315                                 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
 316                                 reg = <0x42580000 0x1000>;
 317                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 318                                 clocks = <&clk IMX93_CLK_LPUART4_GATE>;
 319                                 clock-names = "ipg";
 320                                 status = "disabled";
 321                         };
 322
 323                         lpuart5: serial@42590000 {
 324                                 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
 325                                 reg = <0x42590000 0x1000>;
 326                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 327                                 clocks = <&clk IMX93_CLK_LPUART5_GATE>;
 328                                 clock-names = "ipg";
 329                                 status = "disabled";
 330                         };
 331
 332                         lpuart6: serial@425a0000 {
 333                                 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
 334                                 reg = <0x425a0000 0x1000>;
 335                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 336                                 clocks = <&clk IMX93_CLK_LPUART6_GATE>;
 337                                 clock-names = "ipg";
 338                                 status = "disabled";
 339                         };
 340
 341                         lpuart7: serial@42690000 {
 342                                 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
 343                                 reg = <0x42690000 0x1000>;
 344                                 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
 345                                 clocks = <&clk IMX93_CLK_LPUART7_GATE>;
 346                                 clock-names = "ipg";
 347                                 status = "disabled";
 348                         };
 349
 350                         lpuart8: serial@426a0000 {
 351                                 compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart";
 352                                 reg = <0x426a0000 0x1000>;
 353                                 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
 354                                 clocks = <&clk IMX93_CLK_LPUART8_GATE>;
 355                                 clock-names = "ipg";
 356                                 status = "disabled";
 357                         };
 358
 359                         lpi2c5: i2c@426b0000 {
 360                                 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 361                                 reg = <0x426b0000 0x10000>;
 362                                 #address-cells = <1>;
 363                                 #size-cells = <0>;
 364                                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
 365                                 clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
 366                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 367                                 clock-names = "per", "ipg";
 368                                 status = "disabled";
 369                         };
 370
 371                         lpi2c6: i2c@426c0000 {
 372                                 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 373                                 reg = <0x426c0000 0x10000>;
 374                                 #address-cells = <1>;
 375                                 #size-cells = <0>;
 376                                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
 377                                 clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
 378                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 379                                 clock-names = "per", "ipg";
 380                                 status = "disabled";
 381                         };
 382
 383                         lpi2c7: i2c@426d0000 {
 384                                 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 385                                 reg = <0x426d0000 0x10000>;
 386                                 #address-cells = <1>;
 387                                 #size-cells = <0>;
 388                                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 389                                 clocks = <&clk IMX93_CLK_LPI2C7_GATE>,
 390                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 391                                 clock-names = "per", "ipg";
 392                                 status = "disabled";
 393                         };
 394
 395                         lpi2c8: i2c@426e0000 {
 396                                 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
 397                                 reg = <0x426e0000 0x10000>;
 398                                 #address-cells = <1>;
 399                                 #size-cells = <0>;
 400                                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
 401                                 clocks = <&clk IMX93_CLK_LPI2C8_GATE>,
 402                                          <&clk IMX93_CLK_BUS_WAKEUP>;
 403                                 clock-names = "per", "ipg";
 404                                 status = "disabled";
 405                         };
 406
 407                 };
 408
 409                 aips3: bus@42800000 {
 410                         compatible = "fsl,aips-bus", "simple-bus";
 411                         reg = <0x42800000 0x800000>;
 412                         #address-cells = <1>;
 413                         #size-cells = <1>;
 414                         ranges;
 415
 416                         usdhc1: mmc@42850000 {
 417                                 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
 418                                 reg = <0x42850000 0x10000>;
 419                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 420                                 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
 421                                          <&clk IMX93_CLK_WAKEUP_AXI>,
 422                                          <&clk IMX93_CLK_USDHC1_GATE>;
 423                                 clock-names = "ipg", "ahb", "per";
 424                                 bus-width = <8>;
 425                                 fsl,tuning-start-tap = <20>;
 426                                 fsl,tuning-step= <2>;
 427                                 status = "disabled";
 428                         };
 429
 430                         usdhc2: mmc@42860000 {
 431                                 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
 432                                 reg = <0x42860000 0x10000>;
 433                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 434                                 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
 435                                          <&clk IMX93_CLK_WAKEUP_AXI>,
 436                                          <&clk IMX93_CLK_USDHC2_GATE>;
 437                                 clock-names = "ipg", "ahb", "per";
 438                                 bus-width = <4>;
 439                                 fsl,tuning-start-tap = <20>;
 440                                 fsl,tuning-step= <2>;
 441                                 status = "disabled";
 442                         };
 443
 444                         usdhc3: mmc@428b0000 {
 445                                 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
 446                                 reg = <0x428b0000 0x10000>;
 447                                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 448                                 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
 449                                          <&clk IMX93_CLK_WAKEUP_AXI>,
 450                                          <&clk IMX93_CLK_USDHC3_GATE>;
 451                                 clock-names = "ipg", "ahb", "per";
 452                                 bus-width = <4>;
 453                                 fsl,tuning-start-tap = <20>;
 454                                 fsl,tuning-step= <2>;
 455                                 status = "disabled";
 456                         };
 457                 };
 458
 459                 gpio2: gpio@43810080 {
 460                         compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
 461                         reg = <0x43810080 0x1000>, <0x43810040 0x40>;
 462                         gpio-controller;
 463                         #gpio-cells = <2>;
 464                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 465                         interrupt-controller;
 466                         #interrupt-cells = <2>;
 467                         clocks = <&clk IMX93_CLK_GPIO2_GATE>,
 468                                  <&clk IMX93_CLK_GPIO2_GATE>;
 469                         clock-names = "gpio", "port";
 470                         gpio-ranges = <&iomuxc 0 4 30>;
 471                 };
 472
 473                 gpio3: gpio@43820080 {
 474                         compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
 475                         reg = <0x43820080 0x1000>, <0x43820040 0x40>;
 476                         gpio-controller;
 477                         #gpio-cells = <2>;
 478                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 479                         interrupt-controller;
 480                         #interrupt-cells = <2>;
 481                         clocks = <&clk IMX93_CLK_GPIO3_GATE>,
 482                                  <&clk IMX93_CLK_GPIO3_GATE>;
 483                         clock-names = "gpio", "port";
 484                         gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>,
 485                                       <&iomuxc 26 34 2>, <&iomuxc 28 0 4>;
 486                 };
 487
 488                 gpio4: gpio@43830080 {
 489                         compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
 490                         reg = <0x43830080 0x1000>, <0x43830040 0x40>;
 491                         gpio-controller;
 492                         #gpio-cells = <2>;
 493                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 494                         interrupt-controller;
 495                         #interrupt-cells = <2>;
 496                         clocks = <&clk IMX93_CLK_GPIO4_GATE>,
 497                                  <&clk IMX93_CLK_GPIO4_GATE>;
 498                         clock-names = "gpio", "port";
 499                         gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>;
 500                 };
 501
 502                 gpio1: gpio@47400080 {
 503                         compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio";
 504                         reg = <0x47400080 0x1000>, <0x47400040 0x40>;
 505                         gpio-controller;
 506                         #gpio-cells = <2>;
 507                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 508                         interrupt-controller;
 509                         #interrupt-cells = <2>;
 510                         clocks = <&clk IMX93_CLK_GPIO1_GATE>,
 511                                  <&clk IMX93_CLK_GPIO1_GATE>;
 512                         clock-names = "gpio", "port";
 513                         gpio-ranges = <&iomuxc 0 92 16>;
 514                 };
 515
 516                 s4muap: mailbox@47520000 {
 517                         compatible = "fsl,imx93-mu-s4";
 518                         reg = <0x47520000 0x10000>;
 519                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 520                                      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 521                         interrupt-names = "tx", "rx";
 522                         #mbox-cells = <2>;
 523                 };
 524
 525                 media_blk_ctrl: system-controller@4ac10000 {
 526                         compatible = "fsl,imx93-media-blk-ctrl", "syscon";
 527                         reg = <0x4ac10000 0x10000>;
 528                         power-domains = <&mediamix>;
 529                         clocks = <&clk IMX93_CLK_MEDIA_APB>,
 530                                  <&clk IMX93_CLK_MEDIA_AXI>,
 531                                  <&clk IMX93_CLK_NIC_MEDIA_GATE>,
 532                                  <&clk IMX93_CLK_MEDIA_DISP_PIX>,
 533                                  <&clk IMX93_CLK_CAM_PIX>,
 534                                  <&clk IMX93_CLK_PXP_GATE>,
 535                                  <&clk IMX93_CLK_LCDIF_GATE>,
 536                                  <&clk IMX93_CLK_ISI_GATE>,
 537                                  <&clk IMX93_CLK_MIPI_CSI_GATE>,
 538                                  <&clk IMX93_CLK_MIPI_DSI_GATE>;
 539                         clock-names = "apb", "axi", "nic", "disp", "cam",
 540                                       "pxp", "lcdif", "isi", "csi", "dsi";
 541                         #power-domain-cells = <1>;
 542                         status = "disabled";
 543                 };
 544         };
 545 };