arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2022 NXP
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "imx93.dtsi"
   9
  10 / {
  11         model = "NXP i.MX93 11X11 EVK board";
  12         compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
  13
  14         chosen {
  15                 stdout-path = &lpuart1;
  16         };
  17
  18         reg_usdhc2_vmmc: regulator-usdhc2 {
  19                 compatible = "regulator-fixed";
  20                 pinctrl-names = "default";
  21                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  22                 regulator-name = "VSD_3V3";
  23                 regulator-min-microvolt = <3300000>;
  24                 regulator-max-microvolt = <3300000>;
  25                 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
  26                 enable-active-high;
  27         };
  28 };
  29
  30 &mu1 {
  31         status = "okay";
  32 };
  33
  34 &mu2 {
  35         status = "okay";
  36 };
  37
  38 &lpuart1 { /* console */
  39         pinctrl-names = "default";
  40         pinctrl-0 = <&pinctrl_uart1>;
  41         status = "okay";
  42 };
  43
  44 &usdhc1 {
  45         pinctrl-names = "default", "state_100mhz", "state_200mhz";
  46         pinctrl-0 = <&pinctrl_usdhc1>;
  47         pinctrl-1 = <&pinctrl_usdhc1>;
  48         pinctrl-2 = <&pinctrl_usdhc1>;
  49         bus-width = <8>;
  50         non-removable;
  51         status = "okay";
  52 };
  53
  54 &usdhc2 {
  55         pinctrl-names = "default", "state_100mhz", "state_200mhz";
  56         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  57         pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  58         pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  59         cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
  60         vmmc-supply = <&reg_usdhc2_vmmc>;
  61         bus-width = <4>;
  62         status = "okay";
  63         no-sdio;
  64         no-mmc;
  65 };
  66
  67 &iomuxc {
  68         pinctrl_uart1: uart1grp {
  69                 fsl,pins = <
  70                         MX93_PAD_UART1_RXD__LPUART1_RX                  0x31e
  71                         MX93_PAD_UART1_TXD__LPUART1_TX                  0x31e
  72                 >;
  73         };
  74
  75         pinctrl_usdhc1: usdhc1grp {
  76                 fsl,pins = <
  77                         MX93_PAD_SD1_CLK__USDHC1_CLK            0x15fe
  78                         MX93_PAD_SD1_CMD__USDHC1_CMD            0x13fe
  79                         MX93_PAD_SD1_DATA0__USDHC1_DATA0        0x13fe
  80                         MX93_PAD_SD1_DATA1__USDHC1_DATA1        0x13fe
  81                         MX93_PAD_SD1_DATA2__USDHC1_DATA2        0x13fe
  82                         MX93_PAD_SD1_DATA3__USDHC1_DATA3        0x13fe
  83                         MX93_PAD_SD1_DATA4__USDHC1_DATA4        0x13fe
  84                         MX93_PAD_SD1_DATA5__USDHC1_DATA5        0x13fe
  85                         MX93_PAD_SD1_DATA6__USDHC1_DATA6        0x13fe
  86                         MX93_PAD_SD1_DATA7__USDHC1_DATA7        0x13fe
  87                         MX93_PAD_SD1_STROBE__USDHC1_STROBE      0x15fe
  88                 >;
  89         };
  90
  91         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
  92                 fsl,pins = <
  93                         MX93_PAD_SD2_RESET_B__GPIO3_IO07        0x31e
  94                 >;
  95         };
  96
  97         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
  98                 fsl,pins = <
  99                         MX93_PAD_SD2_CD_B__GPIO3_IO00           0x31e
 100                 >;
 101         };
 102
 103         pinctrl_usdhc2: usdhc2grp {
 104                 fsl,pins = <
 105                         MX93_PAD_SD2_CLK__USDHC2_CLK            0x15fe
 106                         MX93_PAD_SD2_CMD__USDHC2_CMD            0x13fe
 107                         MX93_PAD_SD2_DATA0__USDHC2_DATA0        0x13fe
 108                         MX93_PAD_SD2_DATA1__USDHC2_DATA1        0x13fe
 109                         MX93_PAD_SD2_DATA2__USDHC2_DATA2        0x13fe
 110                         MX93_PAD_SD2_DATA3__USDHC2_DATA3        0x13fe
 111                         MX93_PAD_SD2_VSELECT__USDHC2_VSELECT    0x51e
 112                 >;
 113         };
 114 };