arch/arm64/boot/dts/freescale/imx8ulp.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2021 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8ulp-clock.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/power/imx8ulp-power.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 #include "imx8ulp-pinfunc.h"
  13
  14 / {
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 ethernet0 = &fec;
  21                 gpio0 = &gpiod;
  22                 gpio1 = &gpioe;
  23                 gpio2 = &gpiof;
  24                 mmc0 = &usdhc0;
  25                 mmc1 = &usdhc1;
  26                 mmc2 = &usdhc2;
  27                 serial0 = &lpuart4;
  28                 serial1 = &lpuart5;
  29                 serial2 = &lpuart6;
  30                 serial3 = &lpuart7;
  31         };
  32
  33         cpus {
  34                 #address-cells = <2>;
  35                 #size-cells = <0>;
  36
  37                 A35_0: cpu@0 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a35";
  40                         reg = <0x0 0x0>;
  41                         enable-method = "psci";
  42                         next-level-cache = <&A35_L2>;
  43                         cpu-idle-states = <&cpu_sleep>;
  44                 };
  45
  46                 A35_1: cpu@1 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a35";
  49                         reg = <0x0 0x1>;
  50                         enable-method = "psci";
  51                         next-level-cache = <&A35_L2>;
  52                         cpu-idle-states = <&cpu_sleep>;
  53                 };
  54
  55                 A35_L2: l2-cache0 {
  56                         compatible = "cache";
  57                         cache-level = <2>;
  58                         cache-unified;
  59                 };
  60
  61                 idle-states {
  62                         entry-method = "psci";
  63
  64                         cpu_sleep: cpu-sleep {
  65                                 compatible = "arm,idle-state";
  66                                 arm,psci-suspend-param = <0x0>;
  67                                 local-timer-stop;
  68                                 entry-latency-us = <1000>;
  69                                 exit-latency-us = <700>;
  70                                 min-residency-us = <2700>;
  71                         };
  72                 };
  73         };
  74
  75         gic: interrupt-controller@2d400000 {
  76                 compatible = "arm,gic-v3";
  77                 reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
  78                       <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
  79                 #interrupt-cells = <3>;
  80                 interrupt-controller;
  81                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  82         };
  83
  84         pmu {
  85                 compatible = "arm,cortex-a35-pmu";
  86                 interrupt-parent = <&gic>;
  87                 interrupts = <GIC_PPI 7
  88                              (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  89                 interrupt-affinity = <&A35_0>, <&A35_1>;
  90         };
  91
  92         psci {
  93                 compatible = "arm,psci-1.0";
  94                 method = "smc";
  95         };
  96
  97         thermal-zones {
  98                 cpu-thermal {
  99                         polling-delay-passive = <250>;
 100                         polling-delay = <2000>;
 101                         thermal-sensors = <&scmi_sensor 0>;
 102
 103                         trips {
 104                                 cpu_alert0: trip0 {
 105                                         temperature = <85000>;
 106                                         hysteresis = <2000>;
 107                                         type = "passive";
 108                                 };
 109
 110                                 cpu_crit0: trip1 {
 111                                         temperature = <95000>;
 112                                         hysteresis = <2000>;
 113                                         type = "critical";
 114                                 };
 115                         };
 116                 };
 117         };
 118
 119         timer {
 120                 compatible = "arm,armv8-timer";
 121                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
 122                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
 123                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
 124                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
 125         };
 126
 127         frosc: clock-frosc {
 128                 compatible = "fixed-clock";
 129                 clock-frequency = <192000000>;
 130                 clock-output-names = "frosc";
 131                 #clock-cells = <0>;
 132         };
 133
 134         lposc: clock-lposc {
 135                 compatible = "fixed-clock";
 136                 clock-frequency = <1000000>;
 137                 clock-output-names = "lposc";
 138                 #clock-cells = <0>;
 139         };
 140
 141         rosc: clock-rosc {
 142                 compatible = "fixed-clock";
 143                 clock-frequency = <32768>;
 144                 clock-output-names = "rosc";
 145                 #clock-cells = <0>;
 146         };
 147
 148         sosc: clock-sosc {
 149                 compatible = "fixed-clock";
 150                 clock-frequency = <24000000>;
 151                 clock-output-names = "sosc";
 152                 #clock-cells = <0>;
 153         };
 154
 155         sram@2201f000 {
 156                 compatible = "mmio-sram";
 157                 reg = <0x0 0x2201f000 0x0 0x1000>;
 158
 159                 #address-cells = <1>;
 160                 #size-cells = <1>;
 161                 ranges = <0 0x0 0x2201f000 0x1000>;
 162
 163                 scmi_buf: scmi-sram-section@0 {
 164                         compatible = "arm,scmi-shmem";
 165                         reg = <0x0 0x400>;
 166                 };
 167         };
 168
 169         firmware {
 170                 scmi {
 171                         compatible = "arm,scmi-smc";
 172                         arm,smc-id = <0xc20000fe>;
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175                         shmem = <&scmi_buf>;
 176
 177                         scmi_devpd: protocol@11 {
 178                                 reg = <0x11>;
 179                                 #power-domain-cells = <1>;
 180                         };
 181
 182                         scmi_sensor: protocol@15 {
 183                                 reg = <0x15>;
 184                                 #thermal-sensor-cells = <1>;
 185                         };
 186                 };
 187         };
 188
 189         cm33: remoteproc-cm33 {
 190                 compatible = "fsl,imx8ulp-cm33";
 191                 status = "disabled";
 192         };
 193
 194         soc: soc@0 {
 195                 compatible = "simple-bus";
 196                 #address-cells = <1>;
 197                 #size-cells = <1>;
 198                 ranges = <0x0 0x0 0x0 0x40000000>,
 199                          <0x60000000 0x0 0x60000000 0x1000000>;
 200
 201                 s4muap: mailbox@27020000 {
 202                         compatible = "fsl,imx8ulp-mu-s4";
 203                         reg = <0x27020000 0x10000>;
 204                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 205                         #mbox-cells = <2>;
 206                 };
 207
 208                 per_bridge3: bus@29000000 {
 209                         compatible = "simple-bus";
 210                         reg = <0x29000000 0x800000>;
 211                         #address-cells = <1>;
 212                         #size-cells = <1>;
 213                         ranges;
 214
 215                         mu: mailbox@29220000 {
 216                                 compatible = "fsl,imx8ulp-mu";
 217                                 reg = <0x29220000 0x10000>;
 218                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 219                                 #mbox-cells = <2>;
 220                                 status = "disabled";
 221                         };
 222
 223                         mu3: mailbox@29230000 {
 224                                 compatible = "fsl,imx8ulp-mu";
 225                                 reg = <0x29230000 0x10000>;
 226                                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 227                                 clocks = <&pcc3 IMX8ULP_CLK_MU3_A>;
 228                                 #mbox-cells = <2>;
 229                                 status = "disabled";
 230                         };
 231
 232                         wdog3: watchdog@292a0000 {
 233                                 compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
 234                                 reg = <0x292a0000 0x10000>;
 235                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 236                                 clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
 237                                 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
 238                                 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
 239                                 timeout-sec = <40>;
 240                         };
 241
 242                         cgc1: clock-controller@292c0000 {
 243                                 compatible = "fsl,imx8ulp-cgc1";
 244                                 reg = <0x292c0000 0x10000>;
 245                                 #clock-cells = <1>;
 246                         };
 247
 248                         pcc3: clock-controller@292d0000 {
 249                                 compatible = "fsl,imx8ulp-pcc3";
 250                                 reg = <0x292d0000 0x10000>;
 251                                 #clock-cells = <1>;
 252                                 #reset-cells = <1>;
 253                         };
 254
 255                         tpm5: tpm@29340000 {
 256                                 compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
 257                                 reg = <0x29340000 0x1000>;
 258                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 259                                 clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
 260                                          <&pcc3 IMX8ULP_CLK_TPM5>;
 261                                 clock-names = "ipg", "per";
 262                                 status = "disabled";
 263                         };
 264
 265                         lpi2c4: i2c@29370000 {
 266                                 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
 267                                 reg = <0x29370000 0x10000>;
 268                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 269                                 clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
 270                                          <&pcc3 IMX8ULP_CLK_LPI2C4>;
 271                                 clock-names = "per", "ipg";
 272                                 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
 273                                 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
 274                                 assigned-clock-rates = <48000000>;
 275                                 status = "disabled";
 276                         };
 277
 278                         lpi2c5: i2c@29380000 {
 279                                 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
 280                                 reg = <0x29380000 0x10000>;
 281                                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 282                                 clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
 283                                          <&pcc3 IMX8ULP_CLK_LPI2C5>;
 284                                 clock-names = "per", "ipg";
 285                                 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
 286                                 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
 287                                 assigned-clock-rates = <48000000>;
 288                                 status = "disabled";
 289                         };
 290
 291                         lpuart4: serial@29390000 {
 292                                 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 293                                 reg = <0x29390000 0x1000>;
 294                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 295                                 clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
 296                                 clock-names = "ipg";
 297                                 status = "disabled";
 298                         };
 299
 300                         lpuart5: serial@293a0000 {
 301                                 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 302                                 reg = <0x293a0000 0x1000>;
 303                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 304                                 clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
 305                                 clock-names = "ipg";
 306                                 status = "disabled";
 307                         };
 308
 309                         lpspi4: spi@293b0000 {
 310                                 #address-cells = <1>;
 311                                 #size-cells = <0>;
 312                                 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
 313                                 reg = <0x293b0000 0x10000>;
 314                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 315                                 clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
 316                                          <&pcc3 IMX8ULP_CLK_LPSPI4>;
 317                                 clock-names = "per", "ipg";
 318                                 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
 319                                 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
 320                                 assigned-clock-rates = <48000000>;
 321                                 status = "disabled";
 322                         };
 323
 324                         lpspi5: spi@293c0000 {
 325                                 #address-cells = <1>;
 326                                 #size-cells = <0>;
 327                                 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
 328                                 reg = <0x293c0000 0x10000>;
 329                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 330                                 clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
 331                                          <&pcc3 IMX8ULP_CLK_LPSPI5>;
 332                                 clock-names = "per", "ipg";
 333                                 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
 334                                 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
 335                                 assigned-clock-rates = <48000000>;
 336                                 status = "disabled";
 337                         };
 338                 };
 339
 340                 per_bridge4: bus@29800000 {
 341                         compatible = "simple-bus";
 342                         reg = <0x29800000 0x800000>;
 343                         #address-cells = <1>;
 344                         #size-cells = <1>;
 345                         ranges;
 346
 347                         pcc4: clock-controller@29800000 {
 348                                 compatible = "fsl,imx8ulp-pcc4";
 349                                 reg = <0x29800000 0x10000>;
 350                                 #clock-cells = <1>;
 351                                 #reset-cells = <1>;
 352                         };
 353
 354                         flexspi2: spi@29810000 {
 355                                 compatible = "nxp,imx8mm-fspi";
 356                                 reg = <0x29810000 0x10000>, <0x60000000 0x10000000>;
 357                                 reg-names = "fspi_base", "fspi_mmap";
 358                                 #address-cells = <1>;
 359                                 #size-cells = <0>;
 360                                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 361                                 clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>,
 362                                          <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
 363                                 clock-names = "fspi_en", "fspi";
 364                                 assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
 365                                 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
 366                                 status = "disabled";
 367                         };
 368
 369                         lpi2c6: i2c@29840000 {
 370                                 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
 371                                 reg = <0x29840000 0x10000>;
 372                                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 373                                 clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
 374                                          <&pcc4 IMX8ULP_CLK_LPI2C6>;
 375                                 clock-names = "per", "ipg";
 376                                 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
 377                                 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
 378                                 assigned-clock-rates = <48000000>;
 379                                 status = "disabled";
 380                         };
 381
 382                         lpi2c7: i2c@29850000 {
 383                                 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
 384                                 reg = <0x29850000 0x10000>;
 385                                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 386                                 clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
 387                                          <&pcc4 IMX8ULP_CLK_LPI2C7>;
 388                                 clock-names = "per", "ipg";
 389                                 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
 390                                 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
 391                                 assigned-clock-rates = <48000000>;
 392                                 status = "disabled";
 393                         };
 394
 395                         lpuart6: serial@29860000 {
 396                                 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 397                                 reg = <0x29860000 0x1000>;
 398                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 399                                 clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
 400                                 clock-names = "ipg";
 401                                 status = "disabled";
 402                         };
 403
 404                         lpuart7: serial@29870000 {
 405                                 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 406                                 reg = <0x29870000 0x1000>;
 407                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 408                                 clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
 409                                 clock-names = "ipg";
 410                                 status = "disabled";
 411                         };
 412
 413                         iomuxc1: pinctrl@298c0000 {
 414                                 compatible = "fsl,imx8ulp-iomuxc1";
 415                                 reg = <0x298c0000 0x10000>;
 416                         };
 417
 418                         usdhc0: mmc@298d0000 {
 419                                 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
 420                                 reg = <0x298d0000 0x10000>;
 421                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 422                                 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
 423                                          <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
 424                                          <&pcc4 IMX8ULP_CLK_USDHC0>;
 425                                 clock-names = "ipg", "ahb", "per";
 426                                 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
 427                                 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>,
 428                                                   <&pcc4 IMX8ULP_CLK_USDHC0>;
 429                                 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>;
 430                                 assigned-clock-rates = <389283840>, <389283840>;
 431                                 fsl,tuning-start-tap = <20>;
 432                                 fsl,tuning-step = <2>;
 433                                 bus-width = <4>;
 434                                 status = "disabled";
 435                         };
 436
 437                         usdhc1: mmc@298e0000 {
 438                                 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
 439                                 reg = <0x298e0000 0x10000>;
 440                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 441                                 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
 442                                          <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
 443                                          <&pcc4 IMX8ULP_CLK_USDHC1>;
 444                                 clock-names = "ipg", "ahb", "per";
 445                                 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
 446                                 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>,
 447                                                   <&pcc4 IMX8ULP_CLK_USDHC1>;
 448                                 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
 449                                 assigned-clock-rates = <194641920>, <194641920>;
 450                                 fsl,tuning-start-tap = <20>;
 451                                 fsl,tuning-step = <2>;
 452                                 bus-width = <4>;
 453                                 status = "disabled";
 454                         };
 455
 456                         usdhc2: mmc@298f0000 {
 457                                 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
 458                                 reg = <0x298f0000 0x10000>;
 459                                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 460                                 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
 461                                          <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
 462                                          <&pcc4 IMX8ULP_CLK_USDHC2>;
 463                                 clock-names = "ipg", "ahb", "per";
 464                                 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
 465                                 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>,
 466                                                   <&pcc4 IMX8ULP_CLK_USDHC2>;
 467                                 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
 468                                 assigned-clock-rates = <194641920>, <194641920>;
 469                                 fsl,tuning-start-tap = <20>;
 470                                 fsl,tuning-step = <2>;
 471                                 bus-width = <4>;
 472                                 status = "disabled";
 473                         };
 474
 475                         fec: ethernet@29950000 {
 476                                 compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
 477                                 reg = <0x29950000 0x10000>;
 478                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 479                                 interrupt-names = "int0";
 480                                 fsl,num-tx-queues = <1>;
 481                                 fsl,num-rx-queues = <1>;
 482                                 status = "disabled";
 483                         };
 484                 };
 485
 486                 gpioe: gpio@2d000000 {
 487                                 compatible = "fsl,imx8ulp-gpio";
 488                                 reg = <0x2d000000 0x1000>;
 489                                 gpio-controller;
 490                                 #gpio-cells = <2>;
 491                                 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 492                                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
 493                                 interrupt-controller;
 494                                 #interrupt-cells = <2>;
 495                                 clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
 496                                          <&pcc4 IMX8ULP_CLK_PCTLE>;
 497                                 clock-names = "gpio", "port";
 498                                 gpio-ranges = <&iomuxc1 0 32 24>;
 499                 };
 500
 501                 gpiof: gpio@2d010000 {
 502                                 compatible = "fsl,imx8ulp-gpio";
 503                                 reg = <0x2d010000 0x1000>;
 504                                 gpio-controller;
 505                                 #gpio-cells = <2>;
 506                                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 507                                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 508                                 interrupt-controller;
 509                                 #interrupt-cells = <2>;
 510                                 clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
 511                                          <&pcc4 IMX8ULP_CLK_PCTLF>;
 512                                 clock-names = "gpio", "port";
 513                                 gpio-ranges = <&iomuxc1 0 64 32>;
 514                 };
 515
 516                 per_bridge5: bus@2d800000 {
 517                         compatible = "simple-bus";
 518                         reg = <0x2d800000 0x800000>;
 519                         #address-cells = <1>;
 520                         #size-cells = <1>;
 521                         ranges;
 522
 523                         cgc2: clock-controller@2da60000 {
 524                                 compatible = "fsl,imx8ulp-cgc2";
 525                                 reg = <0x2da60000 0x10000>;
 526                                 #clock-cells = <1>;
 527                         };
 528
 529                         pcc5: clock-controller@2da70000 {
 530                                 compatible = "fsl,imx8ulp-pcc5";
 531                                 reg = <0x2da70000 0x10000>;
 532                                 #clock-cells = <1>;
 533                                 #reset-cells = <1>;
 534                         };
 535                 };
 536
 537                 gpiod: gpio@2e200000 {
 538                         compatible = "fsl,imx8ulp-gpio";
 539                         reg = <0x2e200000 0x1000>;
 540                         gpio-controller;
 541                         #gpio-cells = <2>;
 542                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 543                                      <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
 544                         interrupt-controller;
 545                         #interrupt-cells = <2>;
 546                         clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,
 547                                  <&pcc5 IMX8ULP_CLK_RGPIOD>;
 548                         clock-names = "gpio", "port";
 549                         gpio-ranges = <&iomuxc1 0 0 24>;
 550                 };
 551         };
 552 };