arch/arm64/boot/dts/freescale/imx8ulp.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2021 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8ulp-clock.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/power/imx8ulp-power.h>
  10
  11 #include "imx8ulp-pinfunc.h"
  12
  13 / {
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 ethernet0 = &fec;
  20                 gpio0 = &gpiod;
  21                 gpio1 = &gpioe;
  22                 gpio2 = &gpiof;
  23                 mmc0 = &usdhc0;
  24                 mmc1 = &usdhc1;
  25                 mmc2 = &usdhc2;
  26                 serial0 = &lpuart4;
  27                 serial1 = &lpuart5;
  28                 serial2 = &lpuart6;
  29                 serial3 = &lpuart7;
  30         };
  31
  32         cpus {
  33                 #address-cells = <2>;
  34                 #size-cells = <0>;
  35
  36                 A35_0: cpu@0 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a35";
  39                         reg = <0x0 0x0>;
  40                         enable-method = "psci";
  41                         next-level-cache = <&A35_L2>;
  42                 };
  43
  44                 A35_1: cpu@1 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a35";
  47                         reg = <0x0 0x1>;
  48                         enable-method = "psci";
  49                         next-level-cache = <&A35_L2>;
  50                 };
  51
  52                 A35_L2: l2-cache0 {
  53                         compatible = "cache";
  54                 };
  55         };
  56
  57         gic: interrupt-controller@2d400000 {
  58                 compatible = "arm,gic-v3";
  59                 reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
  60                       <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
  61                 #interrupt-cells = <3>;
  62                 interrupt-controller;
  63                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  64         };
  65
  66         pmu {
  67                 compatible = "arm,cortex-a35-pmu";
  68                 interrupt-parent = <&gic>;
  69                 interrupts = <GIC_PPI 7
  70                              (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  71                 interrupt-affinity = <&A35_0>, <&A35_1>;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-1.0";
  76                 method = "smc";
  77         };
  78
  79         timer {
  80                 compatible = "arm,armv8-timer";
  81                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
  82                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
  83                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
  84                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
  85         };
  86
  87         frosc: clock-frosc {
  88                 compatible = "fixed-clock";
  89                 clock-frequency = <192000000>;
  90                 clock-output-names = "frosc";
  91                 #clock-cells = <0>;
  92         };
  93
  94         lposc: clock-lposc {
  95                 compatible = "fixed-clock";
  96                 clock-frequency = <1000000>;
  97                 clock-output-names = "lposc";
  98                 #clock-cells = <0>;
  99         };
 100
 101         rosc: clock-rosc {
 102                 compatible = "fixed-clock";
 103                 clock-frequency = <32768>;
 104                 clock-output-names = "rosc";
 105                 #clock-cells = <0>;
 106         };
 107
 108         sosc: clock-sosc {
 109                 compatible = "fixed-clock";
 110                 clock-frequency = <24000000>;
 111                 clock-output-names = "sosc";
 112                 #clock-cells = <0>;
 113         };
 114
 115         sram@2201f000 {
 116                 compatible = "mmio-sram";
 117                 reg = <0x0 0x2201f000 0x0 0x1000>;
 118
 119                 #address-cells = <1>;
 120                 #size-cells = <1>;
 121                 ranges = <0 0x0 0x2201f000 0x1000>;
 122
 123                 scmi_buf: scmi-sram-section@0 {
 124                         compatible = "arm,scmi-shmem";
 125                         reg = <0x0 0x400>;
 126                 };
 127         };
 128
 129         firmware {
 130                 scmi {
 131                         compatible = "arm,scmi-smc";
 132                         arm,smc-id = <0xc20000fe>;
 133                         #address-cells = <1>;
 134                         #size-cells = <0>;
 135                         shmem = <&scmi_buf>;
 136
 137                         scmi_devpd: protocol@11 {
 138                                 reg = <0x11>;
 139                                 #power-domain-cells = <1>;
 140                         };
 141
 142                         scmi_sensor: protocol@15 {
 143                                 reg = <0x15>;
 144                                 #thermal-sensor-cells = <1>;
 145                         };
 146                 };
 147         };
 148
 149         soc: soc@0 {
 150                 compatible = "simple-bus";
 151                 #address-cells = <1>;
 152                 #size-cells = <1>;
 153                 ranges = <0x0 0x0 0x0 0x40000000>;
 154
 155                 s4muap: mailbox@27020000 {
 156                         compatible = "fsl,imx8ulp-mu-s4";
 157                         reg = <0x27020000 0x10000>;
 158                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 159                         #mbox-cells = <2>;
 160                 };
 161
 162                 per_bridge3: bus@29000000 {
 163                         compatible = "simple-bus";
 164                         reg = <0x29000000 0x800000>;
 165                         #address-cells = <1>;
 166                         #size-cells = <1>;
 167                         ranges;
 168
 169                         mu: mailbox@29220000 {
 170                                 compatible = "fsl,imx8ulp-mu";
 171                                 reg = <0x29220000 0x10000>;
 172                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 173                                 #mbox-cells = <2>;
 174                                 status = "disabled";
 175                         };
 176
 177                         mu3: mailbox@29230000 {
 178                                 compatible = "fsl,imx8ulp-mu";
 179                                 reg = <0x29230000 0x10000>;
 180                                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 181                                 clocks = <&pcc3 IMX8ULP_CLK_MU3_A>;
 182                                 #mbox-cells = <2>;
 183                                 status = "disabled";
 184                         };
 185
 186                         wdog3: watchdog@292a0000 {
 187                                 compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
 188                                 reg = <0x292a0000 0x10000>;
 189                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 190                                 clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
 191                                 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
 192                                 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
 193                                 timeout-sec = <40>;
 194                         };
 195
 196                         cgc1: clock-controller@292c0000 {
 197                                 compatible = "fsl,imx8ulp-cgc1";
 198                                 reg = <0x292c0000 0x10000>;
 199                                 #clock-cells = <1>;
 200                         };
 201
 202                         pcc3: clock-controller@292d0000 {
 203                                 compatible = "fsl,imx8ulp-pcc3";
 204                                 reg = <0x292d0000 0x10000>;
 205                                 #clock-cells = <1>;
 206                                 #reset-cells = <1>;
 207                         };
 208
 209                         tpm5: tpm@29340000 {
 210                                 compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
 211                                 reg = <0x29340000 0x1000>;
 212                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 213                                 clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
 214                                          <&pcc3 IMX8ULP_CLK_TPM5>;
 215                                 clock-names = "ipg", "per";
 216                                 status = "disabled";
 217                         };
 218
 219                         lpi2c4: i2c@29370000 {
 220                                 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
 221                                 reg = <0x29370000 0x10000>;
 222                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 223                                 clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
 224                                          <&pcc3 IMX8ULP_CLK_LPI2C4>;
 225                                 clock-names = "per", "ipg";
 226                                 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
 227                                 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
 228                                 assigned-clock-rates = <48000000>;
 229                                 status = "disabled";
 230                         };
 231
 232                         lpi2c5: i2c@29380000 {
 233                                 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
 234                                 reg = <0x29380000 0x10000>;
 235                                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 236                                 clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
 237                                          <&pcc3 IMX8ULP_CLK_LPI2C5>;
 238                                 clock-names = "per", "ipg";
 239                                 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
 240                                 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
 241                                 assigned-clock-rates = <48000000>;
 242                                 status = "disabled";
 243                         };
 244
 245                         lpuart4: serial@29390000 {
 246                                 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 247                                 reg = <0x29390000 0x1000>;
 248                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 249                                 clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
 250                                 clock-names = "ipg";
 251                                 status = "disabled";
 252                         };
 253
 254                         lpuart5: serial@293a0000 {
 255                                 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 256                                 reg = <0x293a0000 0x1000>;
 257                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 258                                 clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
 259                                 clock-names = "ipg";
 260                                 status = "disabled";
 261                         };
 262
 263                         lpspi4: spi@293b0000 {
 264                                 #address-cells = <1>;
 265                                 #size-cells = <0>;
 266                                 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
 267                                 reg = <0x293b0000 0x10000>;
 268                                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 269                                 clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
 270                                          <&pcc3 IMX8ULP_CLK_LPSPI4>;
 271                                 clock-names = "per", "ipg";
 272                                 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
 273                                 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
 274                                 assigned-clock-rates = <48000000>;
 275                                 status = "disabled";
 276                         };
 277
 278                         lpspi5: spi@293c0000 {
 279                                 #address-cells = <1>;
 280                                 #size-cells = <0>;
 281                                 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
 282                                 reg = <0x293c0000 0x10000>;
 283                                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 284                                 clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
 285                                          <&pcc3 IMX8ULP_CLK_LPSPI5>;
 286                                 clock-names = "per", "ipg";
 287                                 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
 288                                 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
 289                                 assigned-clock-rates = <48000000>;
 290                                 status = "disabled";
 291                         };
 292                 };
 293
 294                 per_bridge4: bus@29800000 {
 295                         compatible = "simple-bus";
 296                         reg = <0x29800000 0x800000>;
 297                         #address-cells = <1>;
 298                         #size-cells = <1>;
 299                         ranges;
 300
 301                         pcc4: clock-controller@29800000 {
 302                                 compatible = "fsl,imx8ulp-pcc4";
 303                                 reg = <0x29800000 0x10000>;
 304                                 #clock-cells = <1>;
 305                                 #reset-cells = <1>;
 306                         };
 307
 308                         lpi2c6: i2c@29840000 {
 309                                 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
 310                                 reg = <0x29840000 0x10000>;
 311                                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 312                                 clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
 313                                          <&pcc4 IMX8ULP_CLK_LPI2C6>;
 314                                 clock-names = "per", "ipg";
 315                                 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
 316                                 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
 317                                 assigned-clock-rates = <48000000>;
 318                                 status = "disabled";
 319                         };
 320
 321                         lpi2c7: i2c@29850000 {
 322                                 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
 323                                 reg = <0x29850000 0x10000>;
 324                                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 325                                 clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
 326                                          <&pcc4 IMX8ULP_CLK_LPI2C7>;
 327                                 clock-names = "per", "ipg";
 328                                 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
 329                                 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
 330                                 assigned-clock-rates = <48000000>;
 331                                 status = "disabled";
 332                         };
 333
 334                         lpuart6: serial@29860000 {
 335                                 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 336                                 reg = <0x29860000 0x1000>;
 337                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 338                                 clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
 339                                 clock-names = "ipg";
 340                                 status = "disabled";
 341                         };
 342
 343                         lpuart7: serial@29870000 {
 344                                 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 345                                 reg = <0x29870000 0x1000>;
 346                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 347                                 clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
 348                                 clock-names = "ipg";
 349                                 status = "disabled";
 350                         };
 351
 352                         iomuxc1: pinctrl@298c0000 {
 353                                 compatible = "fsl,imx8ulp-iomuxc1";
 354                                 reg = <0x298c0000 0x10000>;
 355                         };
 356
 357                         usdhc0: mmc@298d0000 {
 358                                 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
 359                                 reg = <0x298d0000 0x10000>;
 360                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 361                                 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
 362                                          <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
 363                                          <&pcc4 IMX8ULP_CLK_USDHC0>;
 364                                 clock-names = "ipg", "ahb", "per";
 365                                 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
 366                                 fsl,tuning-start-tap = <20>;
 367                                 fsl,tuning-step = <2>;
 368                                 bus-width = <4>;
 369                                 status = "disabled";
 370                         };
 371
 372                         usdhc1: mmc@298e0000 {
 373                                 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
 374                                 reg = <0x298e0000 0x10000>;
 375                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 376                                 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
 377                                          <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
 378                                          <&pcc4 IMX8ULP_CLK_USDHC1>;
 379                                 clock-names = "ipg", "ahb", "per";
 380                                 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
 381                                 fsl,tuning-start-tap = <20>;
 382                                 fsl,tuning-step = <2>;
 383                                 bus-width = <4>;
 384                                 status = "disabled";
 385                         };
 386
 387                         usdhc2: mmc@298f0000 {
 388                                 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
 389                                 reg = <0x298f0000 0x10000>;
 390                                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 391                                 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
 392                                          <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
 393                                          <&pcc4 IMX8ULP_CLK_USDHC2>;
 394                                 clock-names = "ipg", "ahb", "per";
 395                                 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
 396                                 fsl,tuning-start-tap = <20>;
 397                                 fsl,tuning-step = <2>;
 398                                 bus-width = <4>;
 399                                 status = "disabled";
 400                         };
 401
 402                         fec: ethernet@29950000 {
 403                                 compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
 404                                 reg = <0x29950000 0x10000>;
 405                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 406                                 interrupt-names = "int0";
 407                                 fsl,num-tx-queues = <1>;
 408                                 fsl,num-rx-queues = <1>;
 409                                 status = "disabled";
 410                         };
 411                 };
 412
 413                 gpioe: gpio@2d000080 {
 414                                 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
 415                                 reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
 416                                 gpio-controller;
 417                                 #gpio-cells = <2>;
 418                                 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
 419                                 interrupt-controller;
 420                                 #interrupt-cells = <2>;
 421                                 clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
 422                                          <&pcc4 IMX8ULP_CLK_PCTLE>;
 423                                 clock-names = "gpio", "port";
 424                                 gpio-ranges = <&iomuxc1 0 32 24>;
 425                 };
 426
 427                 gpiof: gpio@2d010080 {
 428                                 compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
 429                                 reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
 430                                 gpio-controller;
 431                                 #gpio-cells = <2>;
 432                                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 433                                 interrupt-controller;
 434                                 #interrupt-cells = <2>;
 435                                 clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
 436                                          <&pcc4 IMX8ULP_CLK_PCTLF>;
 437                                 clock-names = "gpio", "port";
 438                                 gpio-ranges = <&iomuxc1 0 64 32>;
 439                 };
 440
 441                 per_bridge5: bus@2d800000 {
 442                         compatible = "simple-bus";
 443                         reg = <0x2d800000 0x800000>;
 444                         #address-cells = <1>;
 445                         #size-cells = <1>;
 446                         ranges;
 447
 448                         cgc2: clock-controller@2da60000 {
 449                                 compatible = "fsl,imx8ulp-cgc2";
 450                                 reg = <0x2da60000 0x10000>;
 451                                 #clock-cells = <1>;
 452                         };
 453
 454                         pcc5: clock-controller@2da70000 {
 455                                 compatible = "fsl,imx8ulp-pcc5";
 456                                 reg = <0x2da70000 0x10000>;
 457                                 #clock-cells = <1>;
 458                                 #reset-cells = <1>;
 459                         };
 460                 };
 461
 462                 gpiod: gpio@2e200080 {
 463                         compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
 464                         reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
 465                         gpio-controller;
 466                         #gpio-cells = <2>;
 467                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 468                         interrupt-controller;
 469                         #interrupt-cells = <2>;
 470                         clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,
 471                                  <&pcc5 IMX8ULP_CLK_RGPIOD>;
 472                         clock-names = "gpio", "port";
 473                         gpio-ranges = <&iomuxc1 0 0 24>;
 474                 };
 475         };
 476 };