1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "imx8ulp.dtsi"
11 model = "NXP i.MX8ULP EVK";
12 compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
15 stdout-path = &lpuart5;
19 device_type = "memory";
20 reg = <0x0 0x80000000 0 0x80000000>;
29 compatible = "shared-dma-pool";
31 size = <0 0x28000000>;
35 m33_reserved: noncacheable-section@a8600000 {
36 reg = <0 0xa8600000 0 0x1000000>;
40 rsc_table: rsc-table@1fff8000{
41 reg = <0 0x1fff8000 0 0x1000>;
45 vdev0vring0: vdev0vring0@aff00000 {
46 reg = <0 0xaff00000 0 0x8000>;
50 vdev0vring1: vdev0vring1@aff08000 {
51 reg = <0 0xaff08000 0 0x8000>;
55 vdev1vring0: vdev1vring0@aff10000 {
56 reg = <0 0xaff10000 0 0x8000>;
60 vdev1vring1: vdev1vring1@aff18000 {
61 reg = <0 0xaff18000 0 0x8000>;
65 vdevbuffer: vdevbuffer@a8400000 {
66 compatible = "shared-dma-pool";
67 reg = <0 0xa8400000 0 0x100000>;
72 clock_ext_rmii: clock-ext-rmii {
73 compatible = "fixed-clock";
74 clock-frequency = <50000000>;
75 clock-output-names = "ext_rmii_clk";
79 clock_ext_ts: clock-ext-ts {
80 compatible = "fixed-clock";
81 /* External ts clock is 50MHZ from PHY on EVK board. */
82 clock-frequency = <50000000>;
83 clock-output-names = "ext_ts_clk";
89 mbox-names = "tx", "rx", "rxdb";
93 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
94 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
99 pinctrl-names = "default", "sleep";
100 pinctrl-0 = <&pinctrl_flexspi2_ptd>;
101 pinctrl-1 = <&pinctrl_flexspi2_ptd>;
104 mx25uw51345gxdi00: flash@0 {
105 compatible = "jedec,spi-nor";
107 spi-max-frequency = <200000000>;
108 spi-tx-bus-width = <8>;
109 spi-rx-bus-width = <8>;
115 pinctrl-names = "default", "sleep";
116 pinctrl-0 = <&pinctrl_lpuart5>;
117 pinctrl-1 = <&pinctrl_lpuart5>;
122 #address-cells = <1>;
124 clock-frequency = <400000>;
125 pinctrl-names = "default", "sleep";
126 pinctrl-0 = <&pinctrl_lpi2c7>;
127 pinctrl-1 = <&pinctrl_lpi2c7>;
131 compatible = "nxp,pcal9554b";
139 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
140 pinctrl-0 = <&pinctrl_usdhc0>;
141 pinctrl-1 = <&pinctrl_usdhc0>;
142 pinctrl-2 = <&pinctrl_usdhc0>;
143 pinctrl-3 = <&pinctrl_usdhc0>;
150 pinctrl-names = "default", "sleep";
151 pinctrl-0 = <&pinctrl_enet>;
152 pinctrl-1 = <&pinctrl_enet>;
153 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
154 <&pcc4 IMX8ULP_CLK_ENET>,
155 <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
157 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
158 assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
159 assigned-clock-parents = <&clock_ext_ts>;
161 phy-handle = <ðphy>;
165 #address-cells = <1>;
168 ethphy: ethernet-phy@1 {
170 micrel,led-mode = <1>;
180 pinctrl_enet: enetgrp {
182 MX8ULP_PAD_PTE15__ENET0_MDC 0x43
183 MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
184 MX8ULP_PAD_PTE17__ENET0_RXER 0x43
185 MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
186 MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
187 MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
188 MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
189 MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
190 MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
191 MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43
192 MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
196 pinctrl_flexspi2_ptd: flexspi2ptdgrp {
199 MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x42
200 MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x42
201 MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x42
202 MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x42
203 MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x42
204 MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x42
205 MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x42
206 MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x42
207 MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x42
208 MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x42
209 MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x42
213 pinctrl_lpuart5: lpuart5grp {
215 MX8ULP_PAD_PTF14__LPUART5_TX 0x3
216 MX8ULP_PAD_PTF15__LPUART5_RX 0x3
220 pinctrl_lpi2c7: lpi2c7grp {
222 MX8ULP_PAD_PTE12__LPI2C7_SCL 0x20
223 MX8ULP_PAD_PTE13__LPI2C7_SDA 0x20
227 pinctrl_usdhc0: usdhc0grp {
229 MX8ULP_PAD_PTD1__SDHC0_CMD 0x3
230 MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002
231 MX8ULP_PAD_PTD10__SDHC0_D0 0x3
232 MX8ULP_PAD_PTD9__SDHC0_D1 0x3
233 MX8ULP_PAD_PTD8__SDHC0_D2 0x3
234 MX8ULP_PAD_PTD7__SDHC0_D3 0x3
235 MX8ULP_PAD_PTD6__SDHC0_D4 0x3
236 MX8ULP_PAD_PTD5__SDHC0_D5 0x3
237 MX8ULP_PAD_PTD4__SDHC0_D6 0x3
238 MX8ULP_PAD_PTD3__SDHC0_D7 0x3
239 MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002