arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2019 NXP
   4  *      Dong Aisheng <aisheng.dong@nxp.com>
   5  */
   6
   7 &dma_subsys {
   8         uart4_lpcg: clock-controller@5a4a0000 {
   9                 compatible = "fsl,imx8qxp-lpcg";
  10                 reg = <0x5a4a0000 0x10000>;
  11                 #clock-cells = <1>;
  12                 clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>,
  13                          <&dma_ipg_clk>;
  14                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
  15                 clock-output-names = "uart4_lpcg_baud_clk",
  16                                      "uart4_lpcg_ipg_clk";
  17                 power-domains = <&pd IMX_SC_R_UART_4>;
  18         };
  19
  20         can1_lpcg: clock-controller@5ace0000 {
  21                 compatible = "fsl,imx8qxp-lpcg";
  22                 reg = <0x5ace0000 0x10000>;
  23                 #clock-cells = <1>;
  24                 clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>,
  25                          <&dma_ipg_clk>, <&dma_ipg_clk>;
  26                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
  27                 clock-output-names = "can1_lpcg_pe_clk",
  28                                      "can1_lpcg_ipg_clk",
  29                                      "can1_lpcg_chi_clk";
  30                 power-domains = <&pd IMX_SC_R_CAN_1>;
  31         };
  32
  33         can2_lpcg: clock-controller@5acf0000 {
  34                 compatible = "fsl,imx8qxp-lpcg";
  35                 reg = <0x5acf0000 0x10000>;
  36                 #clock-cells = <1>;
  37                 clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>,
  38                          <&dma_ipg_clk>, <&dma_ipg_clk>;
  39                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
  40                 clock-output-names = "can2_lpcg_pe_clk",
  41                                      "can2_lpcg_ipg_clk",
  42                                      "can2_lpcg_chi_clk";
  43                 power-domains = <&pd IMX_SC_R_CAN_2>;
  44         };
  45 };
  46
  47 &edma2 {
  48         reg = <0x5a1f0000 0x170000>;
  49         #dma-cells = <3>;
  50         dma-channels = <22>;
  51         dma-channel-mask = <0xf00>;
  52         interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
  53                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
  54                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
  55                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
  56                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
  57                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
  58                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
  59                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
  60                      <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */
  61                      <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */
  62                      <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */
  63                      <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */
  64                      <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
  65                      <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
  66                      <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
  67                      <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
  68                      <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
  69                      <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
  70                      <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
  71                      <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
  72                      <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
  73                      <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
  74         power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
  75                         <&pd IMX_SC_R_DMA_0_CH1>,
  76                         <&pd IMX_SC_R_DMA_0_CH2>,
  77                         <&pd IMX_SC_R_DMA_0_CH3>,
  78                         <&pd IMX_SC_R_DMA_0_CH4>,
  79                         <&pd IMX_SC_R_DMA_0_CH5>,
  80                         <&pd IMX_SC_R_DMA_0_CH6>,
  81                         <&pd IMX_SC_R_DMA_0_CH7>,
  82                         <&pd IMX_SC_R_DMA_0_CH8>,
  83                         <&pd IMX_SC_R_DMA_0_CH9>,
  84                         <&pd IMX_SC_R_DMA_0_CH10>,
  85                         <&pd IMX_SC_R_DMA_0_CH11>,
  86                         <&pd IMX_SC_R_DMA_0_CH12>,
  87                         <&pd IMX_SC_R_DMA_0_CH13>,
  88                         <&pd IMX_SC_R_DMA_0_CH14>,
  89                         <&pd IMX_SC_R_DMA_0_CH15>,
  90                         <&pd IMX_SC_R_DMA_0_CH16>,
  91                         <&pd IMX_SC_R_DMA_0_CH17>,
  92                         <&pd IMX_SC_R_DMA_0_CH18>,
  93                         <&pd IMX_SC_R_DMA_0_CH19>,
  94                         <&pd IMX_SC_R_DMA_0_CH20>,
  95                         <&pd IMX_SC_R_DMA_0_CH21>;
  96         status = "okay";
  97 };
  98
  99 &edma3 {
 100         power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
 101                      <&pd IMX_SC_R_DMA_1_CH1>,
 102                      <&pd IMX_SC_R_DMA_1_CH2>,
 103                      <&pd IMX_SC_R_DMA_1_CH3>,
 104                      <&pd IMX_SC_R_DMA_1_CH4>,
 105                      <&pd IMX_SC_R_DMA_1_CH5>,
 106                      <&pd IMX_SC_R_DMA_1_CH6>,
 107                      <&pd IMX_SC_R_DMA_1_CH7>;
 108 };
 109
 110 &flexcan1 {
 111         fsl,clk-source = /bits/ 8 <1>;
 112 };
 113
 114 &flexcan2 {
 115         clocks = <&can1_lpcg 1>,
 116                  <&can1_lpcg 0>;
 117         assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>;
 118         fsl,clk-source = /bits/ 8 <1>;
 119 };
 120
 121 &flexcan3 {
 122         clocks = <&can2_lpcg 1>,
 123                  <&can2_lpcg 0>;
 124         assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>;
 125         fsl,clk-source = /bits/ 8 <1>;
 126 };
 127
 128 &lpuart0 {
 129         compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
 130         dmas = <&edma2 13 0 0>, <&edma2 12 0 1>;
 131 };
 132
 133 &lpuart1 {
 134         compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
 135         dmas = <&edma2 15 0 0>, <&edma2 14 0 1>;
 136 };
 137
 138 &lpuart2 {
 139         compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
 140         dmas = <&edma2 17 0 0>, <&edma2 16 0 1>;
 141 };
 142
 143 &lpuart3 {
 144         compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
 145         dmas = <&edma2 19 0 0>, <&edma2 18 0 1>;
 146 };
 147
 148 &i2c0 {
 149         compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
 150 };
 151
 152 &i2c1 {
 153         compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
 154 };
 155
 156 &i2c2 {
 157         compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
 158 };
 159
 160 &i2c3 {
 161         compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
 162 };