arch/arm64/boot/dts/freescale/imx8mq.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2017 NXP
   4  * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   5  */
   6
   7 #include <dt-bindings/clock/imx8mq-clock.h>
   8 #include <dt-bindings/power/imx8mq-power.h>
   9 #include <dt-bindings/reset/imx8mq-reset.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include "dt-bindings/input/input.h"
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14 #include "imx8mq-pinfunc.h"
  15
  16 / {
  17         interrupt-parent = <&gpc>;
  18
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 i2c3 = &i2c4;
  32                 serial0 = &uart1;
  33                 serial1 = &uart2;
  34                 serial2 = &uart3;
  35                 serial3 = &uart4;
  36                 spi0 = &ecspi1;
  37                 spi1 = &ecspi2;
  38                 spi2 = &ecspi3;
  39         };
  40
  41         ckil: clock-ckil {
  42                 compatible = "fixed-clock";
  43                 #clock-cells = <0>;
  44                 clock-frequency = <32768>;
  45                 clock-output-names = "ckil";
  46         };
  47
  48         osc_25m: clock-osc-25m {
  49                 compatible = "fixed-clock";
  50                 #clock-cells = <0>;
  51                 clock-frequency = <25000000>;
  52                 clock-output-names = "osc_25m";
  53         };
  54
  55         osc_27m: clock-osc-27m {
  56                 compatible = "fixed-clock";
  57                 #clock-cells = <0>;
  58                 clock-frequency = <27000000>;
  59                 clock-output-names = "osc_27m";
  60         };
  61
  62         clk_ext1: clock-ext1 {
  63                 compatible = "fixed-clock";
  64                 #clock-cells = <0>;
  65                 clock-frequency = <133000000>;
  66                 clock-output-names = "clk_ext1";
  67         };
  68
  69         clk_ext2: clock-ext2 {
  70                 compatible = "fixed-clock";
  71                 #clock-cells = <0>;
  72                 clock-frequency = <133000000>;
  73                 clock-output-names = "clk_ext2";
  74         };
  75
  76         clk_ext3: clock-ext3 {
  77                 compatible = "fixed-clock";
  78                 #clock-cells = <0>;
  79                 clock-frequency = <133000000>;
  80                 clock-output-names = "clk_ext3";
  81         };
  82
  83         clk_ext4: clock-ext4 {
  84                 compatible = "fixed-clock";
  85                 #clock-cells = <0>;
  86                 clock-frequency= <133000000>;
  87                 clock-output-names = "clk_ext4";
  88         };
  89
  90         cpus {
  91                 #address-cells = <1>;
  92                 #size-cells = <0>;
  93
  94                 A53_0: cpu@0 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a53";
  97                         reg = <0x0>;
  98                         clock-latency = <61036>; /* two CLK32 periods */
  99                         clocks = <&clk IMX8MQ_CLK_ARM>;
 100                         enable-method = "psci";
 101                         next-level-cache = <&A53_L2>;
 102                         operating-points-v2 = <&a53_opp_table>;
 103                         #cooling-cells = <2>;
 104                         nvmem-cells = <&cpu_speed_grade>;
 105                         nvmem-cell-names = "speed_grade";
 106                 };
 107
 108                 A53_1: cpu@1 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a53";
 111                         reg = <0x1>;
 112                         clock-latency = <61036>; /* two CLK32 periods */
 113                         clocks = <&clk IMX8MQ_CLK_ARM>;
 114                         enable-method = "psci";
 115                         next-level-cache = <&A53_L2>;
 116                         operating-points-v2 = <&a53_opp_table>;
 117                         #cooling-cells = <2>;
 118                 };
 119
 120                 A53_2: cpu@2 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a53";
 123                         reg = <0x2>;
 124                         clock-latency = <61036>; /* two CLK32 periods */
 125                         clocks = <&clk IMX8MQ_CLK_ARM>;
 126                         enable-method = "psci";
 127                         next-level-cache = <&A53_L2>;
 128                         operating-points-v2 = <&a53_opp_table>;
 129                         #cooling-cells = <2>;
 130                 };
 131
 132                 A53_3: cpu@3 {
 133                         device_type = "cpu";
 134                         compatible = "arm,cortex-a53";
 135                         reg = <0x3>;
 136                         clock-latency = <61036>; /* two CLK32 periods */
 137                         clocks = <&clk IMX8MQ_CLK_ARM>;
 138                         enable-method = "psci";
 139                         next-level-cache = <&A53_L2>;
 140                         operating-points-v2 = <&a53_opp_table>;
 141                         #cooling-cells = <2>;
 142                 };
 143
 144                 A53_L2: l2-cache0 {
 145                         compatible = "cache";
 146                 };
 147         };
 148
 149         a53_opp_table: opp-table {
 150                 compatible = "operating-points-v2";
 151                 opp-shared;
 152
 153                 opp-800000000 {
 154                         opp-hz = /bits/ 64 <800000000>;
 155                         opp-microvolt = <900000>;
 156                         /* Industrial only */
 157                         opp-supported-hw = <0xf>, <0x4>;
 158                         clock-latency-ns = <150000>;
 159                         opp-suspend;
 160                 };
 161
 162                 opp-1000000000 {
 163                         opp-hz = /bits/ 64 <1000000000>;
 164                         opp-microvolt = <900000>;
 165                         /* Consumer only */
 166                         opp-supported-hw = <0xe>, <0x3>;
 167                         clock-latency-ns = <150000>;
 168                         opp-suspend;
 169                 };
 170
 171                 opp-1300000000 {
 172                         opp-hz = /bits/ 64 <1300000000>;
 173                         opp-microvolt = <1000000>;
 174                         opp-supported-hw = <0xc>, <0x4>;
 175                         clock-latency-ns = <150000>;
 176                         opp-suspend;
 177                 };
 178
 179                 opp-1500000000 {
 180                         opp-hz = /bits/ 64 <1500000000>;
 181                         opp-microvolt = <1000000>;
 182                         opp-supported-hw = <0x8>, <0x3>;
 183                         clock-latency-ns = <150000>;
 184                         opp-suspend;
 185                 };
 186         };
 187
 188         pmu {
 189                 compatible = "arm,cortex-a53-pmu";
 190                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 191                 interrupt-parent = <&gic>;
 192                 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
 193         };
 194
 195         psci {
 196                 compatible = "arm,psci-1.0";
 197                 method = "smc";
 198         };
 199
 200         thermal-zones {
 201                 cpu-thermal {
 202                         polling-delay-passive = <250>;
 203                         polling-delay = <2000>;
 204                         thermal-sensors = <&tmu 0>;
 205
 206                         trips {
 207                                 cpu_alert: cpu-alert {
 208                                         temperature = <80000>;
 209                                         hysteresis = <2000>;
 210                                         type = "passive";
 211                                 };
 212
 213                                 cpu-crit {
 214                                         temperature = <90000>;
 215                                         hysteresis = <2000>;
 216                                         type = "critical";
 217                                 };
 218                         };
 219
 220                         cooling-maps {
 221                                 map0 {
 222                                         trip = <&cpu_alert>;
 223                                         cooling-device =
 224                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 225                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 226                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 227                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 228                                 };
 229                         };
 230                 };
 231
 232                 gpu-thermal {
 233                         polling-delay-passive = <250>;
 234                         polling-delay = <2000>;
 235                         thermal-sensors = <&tmu 1>;
 236
 237                         trips {
 238                                 gpu-crit {
 239                                         temperature = <90000>;
 240                                         hysteresis = <2000>;
 241                                         type = "critical";
 242                                 };
 243                         };
 244                 };
 245
 246                 vpu-thermal {
 247                         polling-delay-passive = <250>;
 248                         polling-delay = <2000>;
 249                         thermal-sensors = <&tmu 2>;
 250
 251                         trips {
 252                                 vpu-crit {
 253                                         temperature = <90000>;
 254                                         hysteresis = <2000>;
 255                                         type = "critical";
 256                                 };
 257                         };
 258                 };
 259         };
 260
 261         timer {
 262                 compatible = "arm,armv8-timer";
 263                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
 264                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
 265                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
 266                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
 267                 interrupt-parent = <&gic>;
 268                 arm,no-tick-in-suspend;
 269         };
 270
 271         soc@0 {
 272                 compatible = "simple-bus";
 273                 #address-cells = <1>;
 274                 #size-cells = <1>;
 275                 ranges = <0x0 0x0 0x0 0x3e000000>;
 276                 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
 277
 278                 bus@30000000 { /* AIPS1 */
 279                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 280                         #address-cells = <1>;
 281                         #size-cells = <1>;
 282                         ranges = <0x30000000 0x30000000 0x400000>;
 283
 284                         gpio1: gpio@30200000 {
 285                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 286                                 reg = <0x30200000 0x10000>;
 287                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 288                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 289                                 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
 290                                 gpio-controller;
 291                                 #gpio-cells = <2>;
 292                                 interrupt-controller;
 293                                 #interrupt-cells = <2>;
 294                                 gpio-ranges = <&iomuxc 0 10 30>;
 295                         };
 296
 297                         gpio2: gpio@30210000 {
 298                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 299                                 reg = <0x30210000 0x10000>;
 300                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 301                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 302                                 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
 303                                 gpio-controller;
 304                                 #gpio-cells = <2>;
 305                                 interrupt-controller;
 306                                 #interrupt-cells = <2>;
 307                                 gpio-ranges = <&iomuxc 0 40 21>;
 308                         };
 309
 310                         gpio3: gpio@30220000 {
 311                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 312                                 reg = <0x30220000 0x10000>;
 313                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 314                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 315                                 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
 316                                 gpio-controller;
 317                                 #gpio-cells = <2>;
 318                                 interrupt-controller;
 319                                 #interrupt-cells = <2>;
 320                                 gpio-ranges = <&iomuxc 0 61 26>;
 321                         };
 322
 323                         gpio4: gpio@30230000 {
 324                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 325                                 reg = <0x30230000 0x10000>;
 326                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 327                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 328                                 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
 329                                 gpio-controller;
 330                                 #gpio-cells = <2>;
 331                                 interrupt-controller;
 332                                 #interrupt-cells = <2>;
 333                                 gpio-ranges = <&iomuxc 0 87 32>;
 334                         };
 335
 336                         gpio5: gpio@30240000 {
 337                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 338                                 reg = <0x30240000 0x10000>;
 339                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 340                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 341                                 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
 342                                 gpio-controller;
 343                                 #gpio-cells = <2>;
 344                                 interrupt-controller;
 345                                 #interrupt-cells = <2>;
 346                                 gpio-ranges = <&iomuxc 0 119 30>;
 347                         };
 348
 349                         tmu: tmu@30260000 {
 350                                 compatible = "fsl,imx8mq-tmu";
 351                                 reg = <0x30260000 0x10000>;
 352                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 353                                 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
 354                                 little-endian;
 355                                 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
 356                                 fsl,tmu-calibration = <0x00000000 0x00000023
 357                                                        0x00000001 0x00000029
 358                                                        0x00000002 0x0000002f
 359                                                        0x00000003 0x00000035
 360                                                        0x00000004 0x0000003d
 361                                                        0x00000005 0x00000043
 362                                                        0x00000006 0x0000004b
 363                                                        0x00000007 0x00000051
 364                                                        0x00000008 0x00000057
 365                                                        0x00000009 0x0000005f
 366                                                        0x0000000a 0x00000067
 367                                                        0x0000000b 0x0000006f
 368
 369                                                        0x00010000 0x0000001b
 370                                                        0x00010001 0x00000023
 371                                                        0x00010002 0x0000002b
 372                                                        0x00010003 0x00000033
 373                                                        0x00010004 0x0000003b
 374                                                        0x00010005 0x00000043
 375                                                        0x00010006 0x0000004b
 376                                                        0x00010007 0x00000055
 377                                                        0x00010008 0x0000005d
 378                                                        0x00010009 0x00000067
 379                                                        0x0001000a 0x00000070
 380
 381                                                        0x00020000 0x00000017
 382                                                        0x00020001 0x00000023
 383                                                        0x00020002 0x0000002d
 384                                                        0x00020003 0x00000037
 385                                                        0x00020004 0x00000041
 386                                                        0x00020005 0x0000004b
 387                                                        0x00020006 0x00000057
 388                                                        0x00020007 0x00000063
 389                                                        0x00020008 0x0000006f
 390
 391                                                        0x00030000 0x00000015
 392                                                        0x00030001 0x00000021
 393                                                        0x00030002 0x0000002d
 394                                                        0x00030003 0x00000039
 395                                                        0x00030004 0x00000045
 396                                                        0x00030005 0x00000053
 397                                                        0x00030006 0x0000005f
 398                                                        0x00030007 0x00000071>;
 399                                 #thermal-sensor-cells =  <1>;
 400                         };
 401
 402                         wdog1: watchdog@30280000 {
 403                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 404                                 reg = <0x30280000 0x10000>;
 405                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 406                                 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
 407                                 status = "disabled";
 408                         };
 409
 410                         wdog2: watchdog@30290000 {
 411                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 412                                 reg = <0x30290000 0x10000>;
 413                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 414                                 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
 415                                 status = "disabled";
 416                         };
 417
 418                         wdog3: watchdog@302a0000 {
 419                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 420                                 reg = <0x302a0000 0x10000>;
 421                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 422                                 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
 423                                 status = "disabled";
 424                         };
 425
 426                         sdma2: sdma@302c0000 {
 427                                 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
 428                                 reg = <0x302c0000 0x10000>;
 429                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 430                                 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
 431                                          <&clk IMX8MQ_CLK_SDMA2_ROOT>;
 432                                 clock-names = "ipg", "ahb";
 433                                 #dma-cells = <3>;
 434                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
 435                         };
 436
 437                         iomuxc: iomuxc@30330000 {
 438                                 compatible = "fsl,imx8mq-iomuxc";
 439                                 reg = <0x30330000 0x10000>;
 440                         };
 441
 442                         iomuxc_gpr: syscon@30340000 {
 443                                 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
 444                                              "syscon", "simple-mfd";
 445                                 reg = <0x30340000 0x10000>;
 446
 447                                 mux: mux-controller {
 448                                         compatible = "mmio-mux";
 449                                         #mux-control-cells = <1>;
 450                                         mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
 451                                 };
 452                         };
 453
 454                         ocotp: ocotp-ctrl@30350000 {
 455                                 compatible = "fsl,imx8mq-ocotp", "syscon";
 456                                 reg = <0x30350000 0x10000>;
 457                                 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
 458                                 #address-cells = <1>;
 459                                 #size-cells = <1>;
 460
 461                                 cpu_speed_grade: speed-grade@10 {
 462                                         reg = <0x10 4>;
 463                                 };
 464                         };
 465
 466                         anatop: syscon@30360000 {
 467                                 compatible = "fsl,imx8mq-anatop", "syscon";
 468                                 reg = <0x30360000 0x10000>;
 469                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 470                         };
 471
 472                         snvs: snvs@30370000 {
 473                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 474                                 reg = <0x30370000 0x10000>;
 475
 476                                 snvs_rtc: snvs-rtc-lp{
 477                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 478                                         regmap =<&snvs>;
 479                                         offset = <0x34>;
 480                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 481                                                 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 482                                         clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
 483                                         clock-names = "snvs-rtc";
 484                                 };
 485
 486                                 snvs_pwrkey: snvs-powerkey {
 487                                         compatible = "fsl,sec-v4.0-pwrkey";
 488                                         regmap = <&snvs>;
 489                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 490                                         linux,keycode = <KEY_POWER>;
 491                                         wakeup-source;
 492                                         status = "disabled";
 493                                 };
 494                         };
 495
 496                         clk: clock-controller@30380000 {
 497                                 compatible = "fsl,imx8mq-ccm";
 498                                 reg = <0x30380000 0x10000>;
 499                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 500                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 501                                 #clock-cells = <1>;
 502                                 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
 503                                          <&clk_ext1>, <&clk_ext2>,
 504                                          <&clk_ext3>, <&clk_ext4>;
 505                                 clock-names = "ckil", "osc_25m", "osc_27m",
 506                                               "clk_ext1", "clk_ext2",
 507                                               "clk_ext3", "clk_ext4";
 508                         };
 509
 510                         src: reset-controller@30390000 {
 511                                 compatible = "fsl,imx8mq-src", "syscon";
 512                                 reg = <0x30390000 0x10000>;
 513                                 #reset-cells = <1>;
 514                         };
 515
 516                         gpc: gpc@303a0000 {
 517                                 compatible = "fsl,imx8mq-gpc";
 518                                 reg = <0x303a0000 0x10000>;
 519                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 520                                 interrupt-parent = <&gic>;
 521                                 interrupt-controller;
 522                                 #interrupt-cells = <3>;
 523
 524                                 pgc {
 525                                         #address-cells = <1>;
 526                                         #size-cells = <0>;
 527
 528                                         pgc_mipi: power-domain@0 {
 529                                                 #power-domain-cells = <0>;
 530                                                 reg = <IMX8M_POWER_DOMAIN_MIPI>;
 531                                         };
 532
 533                                         /*
 534                                          * As per comment in ATF source code:
 535                                          *
 536                                          * PCIE1 and PCIE2 share the
 537                                          * same reset signal, if we
 538                                          * power down PCIE2, PCIE1
 539                                          * will be held in reset too.
 540                                          *
 541                                          * So instead of creating two
 542                                          * separate power domains for
 543                                          * PCIE1 and PCIE2 we create a
 544                                          * link between both and use
 545                                          * it as a shared PCIE power
 546                                          * domain.
 547                                          */
 548                                         pgc_pcie: power-domain@1 {
 549                                                 #power-domain-cells = <0>;
 550                                                 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
 551                                                 power-domains = <&pgc_pcie2>;
 552                                         };
 553
 554                                         pgc_otg1: power-domain@2 {
 555                                                 #power-domain-cells = <0>;
 556                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
 557                                         };
 558
 559                                         pgc_otg2: power-domain@3 {
 560                                                 #power-domain-cells = <0>;
 561                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
 562                                         };
 563
 564                                         pgc_ddr1: power-domain@4 {
 565                                                 #power-domain-cells = <0>;
 566                                                 reg = <IMX8M_POWER_DOMAIN_DDR1>;
 567                                         };
 568
 569                                         pgc_gpu: power-domain@5 {
 570                                                 #power-domain-cells = <0>;
 571                                                 reg = <IMX8M_POWER_DOMAIN_GPU>;
 572                                                 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
 573                                                          <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
 574                                                          <&clk IMX8MQ_CLK_GPU_AXI>,
 575                                                          <&clk IMX8MQ_CLK_GPU_AHB>;
 576                                         };
 577
 578                                         pgc_vpu: power-domain@6 {
 579                                                 #power-domain-cells = <0>;
 580                                                 reg = <IMX8M_POWER_DOMAIN_VPU>;
 581                                         };
 582
 583                                         pgc_disp: power-domain@7 {
 584                                                 #power-domain-cells = <0>;
 585                                                 reg = <IMX8M_POWER_DOMAIN_DISP>;
 586                                         };
 587
 588                                         pgc_mipi_csi1: power-domain@8 {
 589                                                 #power-domain-cells = <0>;
 590                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
 591                                         };
 592
 593                                         pgc_mipi_csi2: power-domain@9 {
 594                                                 #power-domain-cells = <0>;
 595                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
 596                                         };
 597
 598                                         pgc_pcie2: power-domain@a {
 599                                                 #power-domain-cells = <0>;
 600                                                 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
 601                                         };
 602                                 };
 603                         };
 604                 };
 605
 606                 bus@30400000 { /* AIPS2 */
 607                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 608                         #address-cells = <1>;
 609                         #size-cells = <1>;
 610                         ranges = <0x30400000 0x30400000 0x400000>;
 611
 612                         pwm1: pwm@30660000 {
 613                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 614                                 reg = <0x30660000 0x10000>;
 615                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 616                                 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
 617                                          <&clk IMX8MQ_CLK_PWM1_ROOT>;
 618                                 clock-names = "ipg", "per";
 619                                 #pwm-cells = <2>;
 620                                 status = "disabled";
 621                         };
 622
 623                         pwm2: pwm@30670000 {
 624                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 625                                 reg = <0x30670000 0x10000>;
 626                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 627                                 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
 628                                          <&clk IMX8MQ_CLK_PWM2_ROOT>;
 629                                 clock-names = "ipg", "per";
 630                                 #pwm-cells = <2>;
 631                                 status = "disabled";
 632                         };
 633
 634                         pwm3: pwm@30680000 {
 635                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 636                                 reg = <0x30680000 0x10000>;
 637                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 638                                 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
 639                                          <&clk IMX8MQ_CLK_PWM3_ROOT>;
 640                                 clock-names = "ipg", "per";
 641                                 #pwm-cells = <2>;
 642                                 status = "disabled";
 643                         };
 644
 645                         pwm4: pwm@30690000 {
 646                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 647                                 reg = <0x30690000 0x10000>;
 648                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 649                                 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
 650                                          <&clk IMX8MQ_CLK_PWM4_ROOT>;
 651                                 clock-names = "ipg", "per";
 652                                 #pwm-cells = <2>;
 653                                 status = "disabled";
 654                         };
 655
 656                         system_counter: timer@306a0000 {
 657                                 compatible = "nxp,sysctr-timer";
 658                                 reg = <0x306a0000 0x20000>;
 659                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 660                                 clocks = <&osc_25m>;
 661                                 clock-names = "per";
 662                         };
 663                 };
 664
 665                 bus@30800000 { /* AIPS3 */
 666                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 667                         #address-cells = <1>;
 668                         #size-cells = <1>;
 669                         ranges = <0x30800000 0x30800000 0x400000>,
 670                                  <0x08000000 0x08000000 0x10000000>;
 671
 672                         ecspi1: spi@30820000 {
 673                                 #address-cells = <1>;
 674                                 #size-cells = <0>;
 675                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 676                                 reg = <0x30820000 0x10000>;
 677                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 678                                 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
 679                                          <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
 680                                 clock-names = "ipg", "per";
 681                                 status = "disabled";
 682                         };
 683
 684                         ecspi2: spi@30830000 {
 685                                 #address-cells = <1>;
 686                                 #size-cells = <0>;
 687                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 688                                 reg = <0x30830000 0x10000>;
 689                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 690                                 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
 691                                          <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
 692                                 clock-names = "ipg", "per";
 693                                 status = "disabled";
 694                         };
 695
 696                         ecspi3: spi@30840000 {
 697                                 #address-cells = <1>;
 698                                 #size-cells = <0>;
 699                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 700                                 reg = <0x30840000 0x10000>;
 701                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 702                                 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
 703                                          <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
 704                                 clock-names = "ipg", "per";
 705                                 status = "disabled";
 706                         };
 707
 708                         uart1: serial@30860000 {
 709                                 compatible = "fsl,imx8mq-uart",
 710                                              "fsl,imx6q-uart";
 711                                 reg = <0x30860000 0x10000>;
 712                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 713                                 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
 714                                          <&clk IMX8MQ_CLK_UART1_ROOT>;
 715                                 clock-names = "ipg", "per";
 716                                 status = "disabled";
 717                         };
 718
 719                         uart3: serial@30880000 {
 720                                 compatible = "fsl,imx8mq-uart",
 721                                              "fsl,imx6q-uart";
 722                                 reg = <0x30880000 0x10000>;
 723                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 724                                 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
 725                                          <&clk IMX8MQ_CLK_UART3_ROOT>;
 726                                 clock-names = "ipg", "per";
 727                                 status = "disabled";
 728                         };
 729
 730                         uart2: serial@30890000 {
 731                                 compatible = "fsl,imx8mq-uart",
 732                                              "fsl,imx6q-uart";
 733                                 reg = <0x30890000 0x10000>;
 734                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 735                                 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
 736                                          <&clk IMX8MQ_CLK_UART2_ROOT>;
 737                                 clock-names = "ipg", "per";
 738                                 status = "disabled";
 739                         };
 740
 741                         sai2: sai@308b0000 {
 742                                 #sound-dai-cells = <0>;
 743                                 compatible = "fsl,imx8mq-sai";
 744                                 reg = <0x308b0000 0x10000>;
 745                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 746                                 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
 747                                          <&clk IMX8MQ_CLK_SAI2_ROOT>,
 748                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 749                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 750                                 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
 751                                 dma-names = "rx", "tx";
 752                                 status = "disabled";
 753                         };
 754
 755                         crypto: crypto@30900000 {
 756                                 compatible = "fsl,sec-v4.0";
 757                                 #address-cells = <1>;
 758                                 #size-cells = <1>;
 759                                 reg = <0x30900000 0x40000>;
 760                                 ranges = <0 0x30900000 0x40000>;
 761                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 762                                 clocks = <&clk IMX8MQ_CLK_AHB>,
 763                                          <&clk IMX8MQ_CLK_IPG_ROOT>;
 764                                 clock-names = "aclk", "ipg";
 765
 766                                 sec_jr0: jr@1000 {
 767                                         compatible = "fsl,sec-v4.0-job-ring";
 768                                         reg = <0x1000 0x1000>;
 769                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 770                                 };
 771
 772                                 sec_jr1: jr@2000 {
 773                                         compatible = "fsl,sec-v4.0-job-ring";
 774                                         reg = <0x2000 0x1000>;
 775                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 776                                 };
 777
 778                                 sec_jr2: jr@3000 {
 779                                         compatible = "fsl,sec-v4.0-job-ring";
 780                                         reg = <0x3000 0x1000>;
 781                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 782                                 };
 783                         };
 784
 785                         dphy: dphy@30a00300 {
 786                                 compatible = "fsl,imx8mq-mipi-dphy";
 787                                 reg = <0x30a00300 0x100>;
 788                                 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
 789                                 clock-names = "phy_ref";
 790                                 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
 791                                 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
 792                                 assigned-clock-rates = <24000000>;
 793                                 #phy-cells = <0>;
 794                                 power-domains = <&pgc_mipi>;
 795                                 status = "disabled";
 796                         };
 797
 798                         i2c1: i2c@30a20000 {
 799                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 800                                 reg = <0x30a20000 0x10000>;
 801                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 802                                 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
 803                                 #address-cells = <1>;
 804                                 #size-cells = <0>;
 805                                 status = "disabled";
 806                         };
 807
 808                         i2c2: i2c@30a30000 {
 809                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 810                                 reg = <0x30a30000 0x10000>;
 811                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 812                                 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
 813                                 #address-cells = <1>;
 814                                 #size-cells = <0>;
 815                                 status = "disabled";
 816                         };
 817
 818                         i2c3: i2c@30a40000 {
 819                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 820                                 reg = <0x30a40000 0x10000>;
 821                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 822                                 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
 823                                 #address-cells = <1>;
 824                                 #size-cells = <0>;
 825                                 status = "disabled";
 826                         };
 827
 828                         i2c4: i2c@30a50000 {
 829                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 830                                 reg = <0x30a50000 0x10000>;
 831                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 832                                 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
 833                                 #address-cells = <1>;
 834                                 #size-cells = <0>;
 835                                 status = "disabled";
 836                         };
 837
 838                         uart4: serial@30a60000 {
 839                                 compatible = "fsl,imx8mq-uart",
 840                                              "fsl,imx6q-uart";
 841                                 reg = <0x30a60000 0x10000>;
 842                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 843                                 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
 844                                          <&clk IMX8MQ_CLK_UART4_ROOT>;
 845                                 clock-names = "ipg", "per";
 846                                 status = "disabled";
 847                         };
 848
 849                         usdhc1: mmc@30b40000 {
 850                                 compatible = "fsl,imx8mq-usdhc",
 851                                              "fsl,imx7d-usdhc";
 852                                 reg = <0x30b40000 0x10000>;
 853                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 854                                 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
 855                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 856                                          <&clk IMX8MQ_CLK_USDHC1_ROOT>;
 857                                 clock-names = "ipg", "ahb", "per";
 858                                 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
 859                                 assigned-clock-rates = <400000000>;
 860                                 fsl,tuning-start-tap = <20>;
 861                                 fsl,tuning-step = <2>;
 862                                 bus-width = <4>;
 863                                 status = "disabled";
 864                         };
 865
 866                         usdhc2: mmc@30b50000 {
 867                                 compatible = "fsl,imx8mq-usdhc",
 868                                              "fsl,imx7d-usdhc";
 869                                 reg = <0x30b50000 0x10000>;
 870                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 871                                 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
 872                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 873                                          <&clk IMX8MQ_CLK_USDHC2_ROOT>;
 874                                 clock-names = "ipg", "ahb", "per";
 875                                 fsl,tuning-start-tap = <20>;
 876                                 fsl,tuning-step = <2>;
 877                                 bus-width = <4>;
 878                                 status = "disabled";
 879                         };
 880
 881                         qspi0: spi@30bb0000 {
 882                                 #address-cells = <1>;
 883                                 #size-cells = <0>;
 884                                 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
 885                                 reg = <0x30bb0000 0x10000>,
 886                                       <0x08000000 0x10000000>;
 887                                 reg-names = "QuadSPI", "QuadSPI-memory";
 888                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 889                                 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
 890                                          <&clk IMX8MQ_CLK_QSPI_ROOT>;
 891                                 clock-names = "qspi_en", "qspi";
 892                                 status = "disabled";
 893                         };
 894
 895                         sdma1: sdma@30bd0000 {
 896                                 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
 897                                 reg = <0x30bd0000 0x10000>;
 898                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 899                                 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
 900                                          <&clk IMX8MQ_CLK_AHB>;
 901                                 clock-names = "ipg", "ahb";
 902                                 #dma-cells = <3>;
 903                                 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
 904                         };
 905
 906                         fec1: ethernet@30be0000 {
 907                                 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
 908                                 reg = <0x30be0000 0x10000>;
 909                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 910                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 911                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 912                                 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
 913                                          <&clk IMX8MQ_CLK_ENET1_ROOT>,
 914                                          <&clk IMX8MQ_CLK_ENET_TIMER>,
 915                                          <&clk IMX8MQ_CLK_ENET_REF>,
 916                                          <&clk IMX8MQ_CLK_ENET_PHY_REF>;
 917                                 clock-names = "ipg", "ahb", "ptp",
 918                                               "enet_clk_ref", "enet_out";
 919                                 fsl,num-tx-queues = <3>;
 920                                 fsl,num-rx-queues = <3>;
 921                                 status = "disabled";
 922                         };
 923                 };
 924
 925                 bus@32c00000 { /* AIPS4 */
 926                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 927                         #address-cells = <1>;
 928                         #size-cells = <1>;
 929                         ranges = <0x32c00000 0x32c00000 0x400000>;
 930
 931                         irqsteer: interrupt-controller@32e2d000 {
 932                                 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
 933                                 reg = <0x32e2d000 0x1000>;
 934                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 935                                 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
 936                                 clock-names = "ipg";
 937                                 fsl,channel = <0>;
 938                                 fsl,num-irqs = <64>;
 939                                 interrupt-controller;
 940                                 #interrupt-cells = <1>;
 941                         };
 942                 };
 943
 944                 gpu: gpu@38000000 {
 945                         compatible = "vivante,gc";
 946                         reg = <0x38000000 0x40000>;
 947                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 948                         clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
 949                                  <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
 950                                  <&clk IMX8MQ_CLK_GPU_AXI>,
 951                                  <&clk IMX8MQ_CLK_GPU_AHB>;
 952                         clock-names = "core", "shader", "bus", "reg";
 953                         assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
 954                                           <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
 955                                           <&clk IMX8MQ_CLK_GPU_AXI>,
 956                                           <&clk IMX8MQ_CLK_GPU_AHB>,
 957                                           <&clk IMX8MQ_GPU_PLL_BYPASS>;
 958                         assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
 959                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
 960                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
 961                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
 962                                                  <&clk IMX8MQ_GPU_PLL>;
 963                         assigned-clock-rates = <800000000>, <800000000>,
 964                                                <800000000>, <800000000>, <0>;
 965                         power-domains = <&pgc_gpu>;
 966                 };
 967
 968                 usb_dwc3_0: usb@38100000 {
 969                         compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
 970                         reg = <0x38100000 0x10000>;
 971                         clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
 972                                  <&clk IMX8MQ_CLK_USB_CORE_REF>,
 973                                  <&clk IMX8MQ_CLK_32K>;
 974                         clock-names = "bus_early", "ref", "suspend";
 975                         assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
 976                                           <&clk IMX8MQ_CLK_USB_CORE_REF>;
 977                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
 978                                                  <&clk IMX8MQ_SYS1_PLL_100M>;
 979                         assigned-clock-rates = <500000000>, <100000000>;
 980                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 981                         phys = <&usb3_phy0>, <&usb3_phy0>;
 982                         phy-names = "usb2-phy", "usb3-phy";
 983                         power-domains = <&pgc_otg1>;
 984                         usb3-resume-missing-cas;
 985                         status = "disabled";
 986                 };
 987
 988                 usb3_phy0: usb-phy@381f0040 {
 989                         compatible = "fsl,imx8mq-usb-phy";
 990                         reg = <0x381f0040 0x40>;
 991                         clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
 992                         clock-names = "phy";
 993                         assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
 994                         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
 995                         assigned-clock-rates = <100000000>;
 996                         #phy-cells = <0>;
 997                         status = "disabled";
 998                 };
 999
1000                 usb_dwc3_1: usb@38200000 {
1001                         compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1002                         reg = <0x38200000 0x10000>;
1003                         clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
1004                                  <&clk IMX8MQ_CLK_USB_CORE_REF>,
1005                                  <&clk IMX8MQ_CLK_32K>;
1006                         clock-names = "bus_early", "ref", "suspend";
1007                         assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1008                                           <&clk IMX8MQ_CLK_USB_CORE_REF>;
1009                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1010                                                  <&clk IMX8MQ_SYS1_PLL_100M>;
1011                         assigned-clock-rates = <500000000>, <100000000>;
1012                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1013                         phys = <&usb3_phy1>, <&usb3_phy1>;
1014                         phy-names = "usb2-phy", "usb3-phy";
1015                         power-domains = <&pgc_otg2>;
1016                         usb3-resume-missing-cas;
1017                         status = "disabled";
1018                 };
1019
1020                 usb3_phy1: usb-phy@382f0040 {
1021                         compatible = "fsl,imx8mq-usb-phy";
1022                         reg = <0x382f0040 0x40>;
1023                         clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
1024                         clock-names = "phy";
1025                         assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1026                         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1027                         assigned-clock-rates = <100000000>;
1028                         #phy-cells = <0>;
1029                         status = "disabled";
1030                 };
1031
1032                 pcie0: pcie@33800000 {
1033                         compatible = "fsl,imx8mq-pcie";
1034                         reg = <0x33800000 0x400000>,
1035                               <0x1ff00000 0x80000>;
1036                         reg-names = "dbi", "config";
1037                         #address-cells = <3>;
1038                         #size-cells = <2>;
1039                         device_type = "pci";
1040                         bus-range = <0x00 0xff>;
1041                         ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
1042                                   0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1043                         num-lanes = <1>;
1044                         num-viewport = <4>;
1045                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1046                         interrupt-names = "msi";
1047                         #interrupt-cells = <1>;
1048                         interrupt-map-mask = <0 0 0 0x7>;
1049                         interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1050                                         <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1051                                         <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1052                                         <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1053                         fsl,max-link-speed = <2>;
1054                         power-domains = <&pgc_pcie>;
1055                         resets = <&src IMX8MQ_RESET_PCIEPHY>,
1056                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1057                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1058                         reset-names = "pciephy", "apps", "turnoff";
1059                         assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
1060                                           <&clk IMX8MQ_CLK_PCIE1_PHY>,
1061                                           <&clk IMX8MQ_CLK_PCIE1_AUX>;
1062                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1063                                                  <&clk IMX8MQ_SYS2_PLL_100M>,
1064                                                  <&clk IMX8MQ_SYS1_PLL_80M>;
1065                         assigned-clock-rates = <250000000>, <100000000>,
1066                                                <10000000>;
1067                         status = "disabled";
1068                 };
1069
1070                 pcie1: pcie@33c00000 {
1071                         compatible = "fsl,imx8mq-pcie";
1072                         reg = <0x33c00000 0x400000>,
1073                               <0x27f00000 0x80000>;
1074                         reg-names = "dbi", "config";
1075                         #address-cells = <3>;
1076                         #size-cells = <2>;
1077                         device_type = "pci";
1078                         ranges =  <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
1079                                    0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1080                         num-lanes = <1>;
1081                         num-viewport = <4>;
1082                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1083                         interrupt-names = "msi";
1084                         #interrupt-cells = <1>;
1085                         interrupt-map-mask = <0 0 0 0x7>;
1086                         interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1087                                         <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1088                                         <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1089                                         <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1090                         fsl,max-link-speed = <2>;
1091                         power-domains = <&pgc_pcie>;
1092                         resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1093                                  <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1094                                  <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1095                         reset-names = "pciephy", "apps", "turnoff";
1096                         assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
1097                                           <&clk IMX8MQ_CLK_PCIE2_PHY>,
1098                                           <&clk IMX8MQ_CLK_PCIE2_AUX>;
1099                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1100                                                  <&clk IMX8MQ_SYS2_PLL_100M>,
1101                                                  <&clk IMX8MQ_SYS1_PLL_80M>;
1102                         assigned-clock-rates = <250000000>, <100000000>,
1103                                                <10000000>;
1104                         status = "disabled";
1105                 };
1106
1107                 gic: interrupt-controller@38800000 {
1108                         compatible = "arm,gic-v3";
1109                         reg = <0x38800000 0x10000>,     /* GIC Dist */
1110                               <0x38880000 0xc0000>,     /* GICR */
1111                               <0x31000000 0x2000>,      /* GICC */
1112                               <0x31010000 0x2000>,      /* GICV */
1113                               <0x31020000 0x2000>;      /* GICH */
1114                         #interrupt-cells = <3>;
1115                         interrupt-controller;
1116                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1117                         interrupt-parent = <&gic>;
1118                 };
1119
1120                 ddr-pmu@3d800000 {
1121                         compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1122                         reg = <0x3d800000 0x400000>;
1123                         interrupt-parent = <&gic>;
1124                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1125                 };
1126         };
1127 };