1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2019 Zodiac Inflight Innovations
19 compatible = "virtual,mdio-gpio";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>;
22 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>, /* MDC */
23 <&gpio1 14 GPIO_ACTIVE_HIGH>; /* MDIO */
27 phy0: ethernet-phy@0 {
29 reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
33 pcie0_refclk: clock-pcie0-refclk {
34 compatible = "fixed-clock";
36 clock-frequency = <100000000>;
39 pcie1_refclk: clock-pcie1-refclk {
40 compatible = "fixed-clock";
42 clock-frequency = <100000000>;
45 reg_12p0_main: regulator-12p0-main {
46 compatible = "regulator-fixed";
47 regulator-name = "12V_MAIN";
48 regulator-min-microvolt = <12000000>;
49 regulator-max-microvolt = <12000000>;
53 reg_5p0_main: regulator-5p0-main {
54 compatible = "regulator-fixed";
55 vin-supply = <®_12p0_main>;
56 regulator-name = "5V_MAIN";
57 regulator-min-microvolt = <5000000>;
58 regulator-max-microvolt = <5000000>;
62 reg_3p3_main: regulator-3p3-main {
63 compatible = "regulator-fixed";
64 vin-supply = <®_12p0_main>;
65 regulator-name = "3V3_MAIN";
66 regulator-min-microvolt = <3300000>;
67 regulator-max-microvolt = <3300000>;
71 reg_gen_3p3: regulator-gen-3p3 {
72 compatible = "regulator-fixed";
73 vin-supply = <®_3p3_main>;
74 regulator-name = "GEN_3V3";
75 regulator-min-microvolt = <3300000>;
76 regulator-max-microvolt = <3300000>;
80 reg_usdhc2_vmmc: regulator-vsd-3v3 {
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_reg_usdhc2>;
83 compatible = "regulator-fixed";
84 vin-supply = <®_gen_3p3>;
85 regulator-name = "3V3_SD";
86 regulator-min-microvolt = <3300000>;
87 regulator-max-microvolt = <3300000>;
88 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
92 reg_arm: regulator-arm {
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_reg_arm>;
95 compatible = "regulator-gpio";
96 vin-supply = <®_12p0_main>;
97 regulator-name = "0V9_ARM";
98 regulator-min-microvolt = <900000>;
99 regulator-max-microvolt = <1000000>;
100 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
101 states = <1000000 0x1
106 cs2000_ref: cs2000-ref {
107 compatible = "fixed-clock";
109 clock-frequency = <24576000>;
112 cs2000_in_dummy: cs2000-in-dummy {
113 compatible = "fixed-clock";
115 clock-frequency = <0>;
120 cpu-supply = <®_arm>;
124 cpu-supply = <®_arm>;
128 cpu-supply = <®_arm>;
132 cpu-supply = <®_arm>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_fec1>;
139 phy-handle = <&phy0>;
144 #address-cells = <1>;
146 clock-frequency = <12500000>;
151 compatible = "marvell,mv88e6085";
152 pinctrl-0 = <&pinctrl_switch_irq>;
153 pinctrl-names = "default";
156 eeprom-length = <512>;
157 interrupt-parent = <&gpio1>;
158 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
159 interrupt-controller;
160 #interrupt-cells = <2>;
163 #address-cells = <1>;
168 label = "gigabit_proc";
169 phy-handle = <&switchphy0>;
175 phy-handle = <&switchphy1>;
180 phy-mode = "rev-rmii";
192 phy-handle = <&switchphy3>;
198 phy-handle = <&switchphy4>;
203 #address-cells = <1>;
206 switchphy0: switchphy@0 {
208 interrupt-parent = <&switch>;
209 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
212 switchphy1: switchphy@1 {
214 interrupt-parent = <&switch>;
215 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
218 switchphy2: switchphy@2 {
220 interrupt-parent = <&switch>;
221 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
224 switchphy3: switchphy@3 {
226 interrupt-parent = <&switch>;
227 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
230 switchphy4: switchphy@4 {
232 interrupt-parent = <&switch>;
233 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_gpio3_hog>;
246 gpios = <10 GPIO_ACTIVE_HIGH>;
248 line-name = "usb-emulation";
253 gpios = <11 GPIO_ACTIVE_HIGH>;
255 line-name = "usb-mode1";
260 gpios = <12 GPIO_ACTIVE_LOW>;
262 line-name = "usb-pwr-ctrl-en-n";
267 gpios = <13 GPIO_ACTIVE_HIGH>;
269 line-name = "usb-mode2";
274 clock-frequency = <400000>;
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_i2c1>;
280 compatible = "fsl,mma8451";
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_accel>;
284 interrupt-parent = <&gpio3>;
285 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
286 interrupt-names = "INT2";
287 vdd-supply = <®_gen_3p3>;
288 vddio-supply = <®_gen_3p3>;
291 ucs1002: charger@32 {
292 compatible = "microchip,ucs1002";
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_ucs1002>;
296 interrupt-parent = <&gpio3>;
297 interrupts = <17 IRQ_TYPE_EDGE_BOTH>,
298 <18 IRQ_TYPE_EDGE_FALLING>;
299 interrupt-names = "a_det", "alert";
303 compatible = "ti,tpa6130a2";
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_tpa2>;
307 power-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
308 Vdd-supply = <®_5p0_main>;
309 sound-name-prefix = "HPA2";
314 clock-frequency = <400000>;
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_i2c2>;
320 compatible = "fsl,pfuze100";
325 regulator-min-microvolt = <825000>;
326 regulator-max-microvolt = <1100000>;
330 regulator-min-microvolt = <825000>;
331 regulator-max-microvolt = <1100000>;
335 regulator-min-microvolt = <1100000>;
336 regulator-max-microvolt = <1100000>;
341 regulator-min-microvolt = <825000>;
342 regulator-max-microvolt = <1100000>;
347 regulator-min-microvolt = <1800000>;
348 regulator-max-microvolt = <1800000>;
353 regulator-min-microvolt = <5000000>;
354 regulator-max-microvolt = <5150000>;
358 regulator-min-microvolt = <1000000>;
359 regulator-max-microvolt = <3000000>;
368 regulator-min-microvolt = <800000>;
369 regulator-max-microvolt = <1550000>;
373 regulator-min-microvolt = <850000>;
374 regulator-max-microvolt = <975000>;
379 regulator-min-microvolt = <1675000>;
380 regulator-max-microvolt = <1975000>;
385 regulator-min-microvolt = <1625000>;
386 regulator-max-microvolt = <1875000>;
391 regulator-min-microvolt = <3075000>;
392 regulator-max-microvolt = <3625000>;
397 regulator-min-microvolt = <1800000>;
398 regulator-max-microvolt = <3300000>;
404 compatible = "ti,tlv320dac3100";
405 pinctrl-names = "default";
406 pinctrl-0 = <&pinctrl_codec1>;
408 #sound-dai-cells = <0>;
409 HPVDD-supply = <®_gen_3p3>;
410 SPRVDD-supply = <®_gen_3p3>;
411 SPLVDD-supply = <®_gen_3p3>;
412 AVDD-supply = <®_gen_3p3>;
413 IOVDD-supply = <®_gen_3p3>;
414 DVDD-supply = <&vgen4_reg>;
415 reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
419 compatible = "atmel,24c128";
424 compatible = "ti,tpa6130a2";
425 pinctrl-names = "default";
426 pinctrl-0 = <&pinctrl_tpa1>;
428 power-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
429 Vdd-supply = <®_5p0_main>;
430 sound-name-prefix = "HPA1";
434 compatible = "dallas,ds1341";
440 clock-frequency = <100000>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&pinctrl_i2c3>;
446 compatible = "microchip,usb2513b";
447 pinctrl-names = "default";
448 pinctrl-0 = <&pinctrl_usbhub>;
450 reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
454 compatible = "zii,rave-wdt";
459 compatible = "cirrus,cs2000-cp";
462 clock-names = "clk_in", "ref_clk";
463 clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
464 assigned-clocks = <&cs2000>;
465 assigned-clock-rates = <24000000>;
470 clock-frequency = <400000>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&pinctrl_i2c4>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&pinctrl_sai2>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&pinctrl_uart1>;
489 pinctrl-names = "default";
490 pinctrl-0 = <&pinctrl_uart2>;
494 compatible = "zii,rave-sp-rdu2";
495 current-speed = <1000000>;
496 #address-cells = <1>;
500 compatible = "zii,rave-sp-watchdog";
504 compatible = "zii,rave-sp-backlight";
508 compatible = "zii,rave-sp-pwrbutton";
512 compatible = "zii,rave-sp-eeprom";
514 zii,eeprom-name = "dds-eeprom";
518 compatible = "zii,rave-sp-eeprom";
520 #address-cells = <1>;
522 zii,eeprom-name = "main-eeprom";
528 vbus-supply = <&ucs1002>;
534 maximum-speed = "high-speed";
539 vbus-supply = <®_5p0_main>;
545 maximum-speed = "high-speed";
550 pinctrl-names = "default";
551 pinctrl-0 = <&pinctrl_pcie0>;
552 reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
553 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
555 <&clk IMX8MQ_CLK_PCIE1_PHY>,
556 <&clk IMX8MQ_CLK_PCIE1_AUX>;
557 vph-supply = <&vgen5_reg>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&pinctrl_pcie1>;
564 reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
565 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
567 <&clk IMX8MQ_CLK_PCIE2_PHY>,
568 <&clk IMX8MQ_CLK_PCIE2_AUX>;
569 vph-supply = <&vgen5_reg>;
574 power-supply = <&sw1a_reg>;
578 power-supply = <&sw1c_reg>;
582 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
583 assigned-clock-rates = <400000000>;
584 pinctrl-names = "default", "state_100mhz", "state_200mhz";
585 pinctrl-0 = <&pinctrl_usdhc1>;
586 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
587 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
588 vqmmc-supply = <&sw4_reg>;
597 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
598 assigned-clock-rates = <200000000>;
599 pinctrl-names = "default", "state_100mhz", "state_200mhz";
600 pinctrl-0 = <&pinctrl_usdhc2>;
601 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
602 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
603 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
604 vmmc-supply = <®_usdhc2_vmmc>;
613 pinctrl_accel: accelgrp {
615 MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
619 pinctrl_codec1: dac1grp {
621 MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x41
625 pinctrl_fec1: fec1grp {
627 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
628 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
629 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
630 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
631 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
632 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
633 MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x1f
634 MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x91
635 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
636 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
640 pinctrl_fec1_phy_reset: fec1phyresetgrp {
642 MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x11
646 pinctrl_gpio3_hog: gpio3hoggrp {
648 MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x6
649 MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x6
650 MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x6
651 MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x6
655 pinctrl_i2c1: i2c1grp {
657 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000022
658 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000a2
662 pinctrl_i2c2: i2c2grp {
664 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000022
665 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000a2
669 pinctrl_i2c3: i2c3grp {
671 MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000022
672 MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000a2
676 pinctrl_i2c4: i2c4grp {
678 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000022
679 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000a2
683 pinctrl_mdio_bitbang: bitbangmdiogrp {
685 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x44
686 MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x64
690 pinctrl_pcie0: pcie0grp {
692 MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x66
693 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x6
697 pinctrl_pcie1: pcie1grp {
699 MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x66
700 MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x6
704 pinctrl_reg_arm: regarmgrp {
706 MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
710 pinctrl_reg_usdhc2: regusdhc2grp {
712 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
716 pinctrl_sai2: sai2grp {
718 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
719 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
720 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
724 pinctrl_switch_irq: switchgrp {
726 MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
730 pinctrl_tpa1: tpa6130-1grp {
732 MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x41
736 pinctrl_tpa2: tpa6130-2grp {
738 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41
744 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x96
745 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x96
749 pinctrl_uart1: uart1grp {
751 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
752 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
756 pinctrl_uart2: uart2grp {
758 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
759 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
763 pinctrl_ucs1002: ucs1002grp {
765 MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x41
766 MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x41
770 pinctrl_usbhub: usbhubgrp {
772 MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x41
776 pinctrl_usdhc1: usdhc1grp {
778 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
779 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
780 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
781 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
782 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
783 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
784 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
785 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
786 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
787 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
788 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
789 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
793 pinctrl_usdhc1_100mhz: usdhc1-100grp {
795 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
796 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
797 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
798 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
799 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
800 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
801 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
802 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
803 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
804 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
805 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
806 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
810 pinctrl_usdhc1_200mhz: usdhc1-200grp {
812 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
813 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
814 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
815 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
816 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
817 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
818 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
819 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
820 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
821 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
822 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
823 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
827 pinctrl_usdhc2: usdhc2grp {
829 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
830 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
831 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
832 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
833 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
834 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
835 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
839 pinctrl_usdhc2_100mhz: usdhc2-100grp {
841 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
842 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
843 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
844 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
845 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
846 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
847 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
851 pinctrl_usdhc2_200mhz: usdhc2-200grp {
853 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
854 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
855 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
856 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
857 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
858 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
859 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1