1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2019-2021 TQ-Systems GmbH
9 model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ";
10 compatible = "tq,imx8mq-tqma8mq", "fsl,imx8mq";
13 device_type = "memory";
14 /* our minimum RAM config will be 1024 MiB */
15 reg = <0x00000000 0x40000000 0 0x40000000>;
18 /* e-MMC IO, needed for HS modes */
19 reg_vcc1v8: regulator-vcc1v8 {
20 compatible = "regulator-fixed";
21 regulator-name = "TQMA8MX_VCC1V8";
22 regulator-min-microvolt = <1800000>;
23 regulator-max-microvolt = <1800000>;
26 reg_vcc3v3: regulator-vcc3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "TQMA8MX_VCC3V3";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
33 reg_vdd_arm: regulator-vdd-arm {
34 compatible = "regulator-gpio";
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_dvfs>;
37 regulator-min-microvolt = <900000>;
38 regulator-max-microvolt = <1000000>;
39 regulator-name = "TQMa8Mx_DVFS";
40 regulator-type = "voltage";
41 regulator-settling-time-us = <150000>;
42 gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
43 states = <900000 0x1 1000000 0x0>;
51 /* global autoconfigured region for contiguous allocations */
53 compatible = "shared-dma-pool";
56 size = <0 0x28000000>;
57 /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
58 alloc-ranges = <0 0x40000000 0 0x78000000>;
65 cpu-supply = <®_vdd_arm>;
69 cpu-supply = <®_vdd_arm>;
73 cpu-supply = <®_vdd_arm>;
77 cpu-supply = <®_vdd_arm>;
85 power-supply = <&sw1a_reg>;
89 power-supply = <&sw1c_reg>;
93 clock-frequency = <100000>;
94 pinctrl-names = "default", "gpio";
95 pinctrl-0 = <&pinctrl_i2c1>;
96 pinctrl-1 = <&pinctrl_i2c1_gpio>;
97 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
98 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
102 compatible = "fsl,pfuze100";
103 fsl,pfuze-support-disable-sw;
109 regulator-min-microvolt = <825000>;
110 regulator-max-microvolt = <1100000>;
115 regulator-min-microvolt = <825000>;
116 regulator-max-microvolt = <1100000>;
121 regulator-min-microvolt = <1100000>;
122 regulator-max-microvolt = <1100000>;
128 regulator-min-microvolt = <825000>;
129 regulator-max-microvolt = <1100000>;
133 /* 1.8 V for QSPI NOR, e-MMC IO, must not be changed */
135 regulator-min-microvolt = <1800000>;
136 regulator-max-microvolt = <1800000>;
141 regulator-min-microvolt = <5000000>;
142 regulator-max-microvolt = <5150000>;
146 regulator-min-microvolt = <1000000>;
147 regulator-max-microvolt = <3000000>;
157 regulator-min-microvolt = <800000>;
158 regulator-max-microvolt = <1550000>;
163 regulator-min-microvolt = <850000>;
164 regulator-max-microvolt = <975000>;
170 regulator-min-microvolt = <1675000>;
171 regulator-max-microvolt = <1975000>;
177 regulator-min-microvolt = <1625000>;
178 regulator-max-microvolt = <1875000>;
184 regulator-min-microvolt = <3075000>;
185 regulator-max-microvolt = <3625000>;
191 regulator-min-microvolt = <1800000>;
192 regulator-max-microvolt = <3300000>;
197 sensor0: temperature-sensor@1b {
198 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
203 compatible = "nxp,pcf85063a";
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_rtc>;
207 interrupt-parent = <&gpio1>;
208 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
209 quartz-load-femtofarads = <7000>;
212 compatible = "fixed-clock";
214 clock-frequency = <32768>;
219 compatible = "nxp,se97b", "atmel,24c02";
223 vcc-supply = <®_vcc3v3>;
227 compatible = "atmel,24c64";
230 vcc-supply = <®_vcc3v3>;
235 /* 3.3V supply, only way to switch on internal 1.8V supply using GPR */
236 vph-supply = <&vgen5_reg>;
240 /* 3.3V supply, only way to switch on internal 1.8V supply using GPR */
241 vph-supply = <&vgen5_reg>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_qspi>;
247 assigned-clocks = <&clk IMX8MQ_CLK_QSPI>;
248 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>;
252 compatible = "jedec,spi-nor";
254 #address-cells = <1>;
256 spi-max-frequency = <84000000>;
257 spi-tx-bus-width = <1>;
258 spi-rx-bus-width = <4>;
263 pinctrl-names = "default", "state_100mhz", "state_200mhz";
264 pinctrl-0 = <&pinctrl_usdhc1>;
265 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
266 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
271 vmmc-supply = <®_vcc3v3>;
272 vqmmc-supply = <®_vcc1v8>;
276 /* Attention: wdog reset forcing POR needs baseboard support */
282 pinctrl_dvfs: dvfsgrp {
283 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16>;
286 pinctrl_i2c1: i2c1grp {
287 fsl,pins = <MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f>,
288 <MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f>;
291 pinctrl_i2c1_gpio: i2c1gpiogrp {
292 fsl,pins = <MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000074>,
293 <MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000074>;
296 pinctrl_qspi: qspigrp {
297 fsl,pins = <MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x97>,
298 <MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>,
299 <MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x97>,
300 <MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x97>,
301 <MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x97>,
302 <MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x97>;
305 pinctrl_rtc: rtcgrp {
306 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41>;
309 pinctrl_usdhc1: usdhc1grp {
310 fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83>,
311 <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3>,
312 <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3>,
313 <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3>,
314 <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3>,
315 <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3>,
316 <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3>,
317 <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3>,
318 <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3>,
319 <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3>,
320 <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83>,
321 <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>;
324 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
325 fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85>,
326 <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5>,
327 <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5>,
328 <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5>,
329 <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5>,
330 <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5>,
331 <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5>,
332 <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5>,
333 <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5>,
334 <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5>,
335 <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85>,
336 <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>;
339 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
340 fsl,pins = <MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87>,
341 <MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7>,
342 <MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7>,
343 <MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7>,
344 <MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7>,
345 <MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7>,
346 <MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7>,
347 <MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7>,
348 <MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7>,
349 <MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7>,
350 <MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87>,
351 <MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1>;
354 pinctrl_wdog: wdoggrp {
355 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6>;