1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
12 model = "NXP i.MX8MQ EVK";
13 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
20 device_type = "memory";
21 reg = <0x00000000 0x40000000 0 0xc0000000>;
24 pcie0_refclk: pcie0-refclk {
25 compatible = "fixed-clock";
27 clock-frequency = <100000000>;
30 reg_pcie1: regulator-pcie {
31 compatible = "regulator-fixed";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_pcie1_reg>;
34 regulator-name = "MPCIE_3V3";
35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>;
37 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
41 reg_usdhc2_vmmc: regulator-vsd-3v3 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_reg_usdhc2>;
44 compatible = "regulator-fixed";
45 regulator-name = "VSD_3V3";
46 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <3300000>;
48 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
49 off-on-delay-us = <20000>;
53 buck2_reg: regulator-buck2 {
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_buck2>;
56 compatible = "regulator-gpio";
57 regulator-name = "vdd_arm";
58 regulator-min-microvolt = <900000>;
59 regulator-max-microvolt = <1000000>;
60 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
68 compatible = "gpio-ir-receiver";
69 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_ir>;
72 linux,autosuspend-period = <125>;
75 audio_codec_bt_sco: audio-codec-bt-sco {
76 compatible = "linux,bt-sco";
77 #sound-dai-cells = <1>;
81 #sound-dai-cells = <0>;
82 compatible = "wlf,wm8524";
83 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
87 compatible = "simple-audio-card";
88 simple-audio-card,name = "bt-sco-audio";
89 simple-audio-card,format = "dsp_a";
90 simple-audio-card,bitclock-inversion;
91 simple-audio-card,frame-master = <&btcpu>;
92 simple-audio-card,bitclock-master = <&btcpu>;
94 btcpu: simple-audio-card,cpu {
96 dai-tdm-slot-num = <2>;
97 dai-tdm-slot-width = <16>;
100 simple-audio-card,codec {
101 sound-dai = <&audio_codec_bt_sco 1>;
106 compatible = "simple-audio-card";
107 simple-audio-card,name = "wm8524-audio";
108 simple-audio-card,format = "i2s";
109 simple-audio-card,frame-master = <&cpudai>;
110 simple-audio-card,bitclock-master = <&cpudai>;
111 simple-audio-card,widgets =
112 "Line", "Left Line Out Jack",
113 "Line", "Right Line Out Jack";
114 simple-audio-card,routing =
115 "Left Line Out Jack", "LINEVOUTL",
116 "Right Line Out Jack", "LINEVOUTR";
118 cpudai: simple-audio-card,cpu {
122 link_codec: simple-audio-card,codec {
123 sound-dai = <&wm8524>;
124 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
129 compatible = "fsl,imx-audio-spdif";
131 spdif-controller = <&spdif1>;
137 compatible = "fsl,imx-audio-spdif";
138 model = "imx-hdmi-arc";
139 spdif-controller = <&spdif2>;
145 cpu-supply = <&buck2_reg>;
149 cpu-supply = <&buck2_reg>;
153 cpu-supply = <&buck2_reg>;
157 cpu-supply = <&buck2_reg>;
161 operating-points-v2 = <&ddrc_opp_table>;
164 ddrc_opp_table: opp-table {
165 compatible = "operating-points-v2";
168 opp-hz = /bits/ 64 <25000000>;
172 opp-hz = /bits/ 64 <100000000>;
176 * On imx8mq B0 PLL can't be bypassed so low bus is 166M
179 opp-hz = /bits/ 64 <166935483>;
183 opp-hz = /bits/ 64 <800000000>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_fec1>;
195 phy-mode = "rgmii-id";
196 phy-handle = <ðphy0>;
201 #address-cells = <1>;
204 ethphy0: ethernet-phy@0 {
205 compatible = "ethernet-phy-ieee802.3-c22";
207 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
208 reset-assert-us = <10000>;
209 qca,disable-smarteee;
210 vddio-supply = <&vddh>;
212 vddh: vddh-regulator {
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_wifi_reset>;
224 gpios = <29 GPIO_ACTIVE_HIGH>;
230 clock-frequency = <100000>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_i2c1>;
236 compatible = "fsl,pfuze100";
241 regulator-min-microvolt = <825000>;
242 regulator-max-microvolt = <1100000>;
246 regulator-min-microvolt = <825000>;
247 regulator-max-microvolt = <1100000>;
251 regulator-min-microvolt = <1100000>;
252 regulator-max-microvolt = <1100000>;
257 regulator-min-microvolt = <825000>;
258 regulator-max-microvolt = <1100000>;
263 regulator-min-microvolt = <1800000>;
264 regulator-max-microvolt = <1800000>;
269 regulator-min-microvolt = <5000000>;
270 regulator-max-microvolt = <5150000>;
274 regulator-min-microvolt = <1000000>;
275 regulator-max-microvolt = <3000000>;
284 regulator-min-microvolt = <800000>;
285 regulator-max-microvolt = <1550000>;
289 regulator-min-microvolt = <850000>;
290 regulator-max-microvolt = <975000>;
295 regulator-min-microvolt = <1675000>;
296 regulator-max-microvolt = <1975000>;
301 regulator-min-microvolt = <1625000>;
302 regulator-max-microvolt = <1875000>;
307 regulator-min-microvolt = <3075000>;
308 regulator-max-microvolt = <3625000>;
313 regulator-min-microvolt = <1800000>;
314 regulator-max-microvolt = <3300000>;
325 #address-cells = <1>;
330 pinctrl-0 = <&pinctrl_mipi_dsi>;
331 pinctrl-names = "default";
332 compatible = "raydium,rm67191";
334 reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
339 remote-endpoint = <&mipi_dsi_out>;
347 mipi_dsi_out: endpoint {
348 remote-endpoint = <&panel_in>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_pcie0>;
357 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
358 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
360 <&clk IMX8MQ_CLK_PCIE1_PHY>,
361 <&clk IMX8MQ_CLK_PCIE1_AUX>;
362 vph-supply = <&vgen5_reg>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_pcie1>;
369 reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
370 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
372 <&clk IMX8MQ_CLK_PCIE2_PHY>,
373 <&clk IMX8MQ_CLK_PCIE2_AUX>;
374 vpcie-supply = <®_pcie1>;
375 vph-supply = <&vgen5_reg>;
380 power-supply = <&sw1a_reg>;
384 power-supply = <&sw1c_reg>;
388 pinctrl-names = "default";
389 pinctrl-0 = <&pinctrl_qspi>;
394 #address-cells = <1>;
396 compatible = "micron,n25q256a", "jedec,spi-nor";
397 spi-max-frequency = <29000000>;
398 spi-tx-bus-width = <1>;
399 spi-rx-bus-width = <4>;
404 pinctrl-names = "default";
405 pinctrl-0 = <&pinctrl_sai2>;
406 assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
407 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
408 assigned-clock-rates = <0>, <24576000>;
413 #sound-dai-cells = <0>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&pinctrl_sai3>;
416 assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
417 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
418 assigned-clock-rates = <24576000>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&pinctrl_spdif1>;
429 assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
430 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
431 assigned-clock-rates = <24576000>;
436 assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
437 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
438 assigned-clock-rates = <24576000>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&pinctrl_uart1>;
458 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
459 assigned-clock-rates = <400000000>;
460 pinctrl-names = "default", "state_100mhz", "state_200mhz";
461 pinctrl-0 = <&pinctrl_usdhc1>;
462 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
463 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
464 vqmmc-supply = <&sw4_reg>;
473 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
474 assigned-clock-rates = <200000000>;
475 pinctrl-names = "default", "state_100mhz", "state_200mhz";
476 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
477 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
478 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
479 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
480 vmmc-supply = <®_usdhc2_vmmc>;
485 pinctrl-names = "default";
486 pinctrl-0 = <&pinctrl_wdog>;
487 fsl,ext-reset-output;
492 pinctrl_buck2: vddarmgrp {
494 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
498 pinctrl_fec1: fec1grp {
500 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
501 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
502 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
503 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
504 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
505 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
506 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
507 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
508 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
509 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
510 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
511 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
512 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
513 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
514 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
518 pinctrl_i2c1: i2c1grp {
520 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
521 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
527 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f
531 pinctrl_mipi_dsi: mipidsigrp {
533 MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
537 pinctrl_pcie0: pcie0grp {
539 MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
540 MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
544 pinctrl_pcie1: pcie1grp {
546 MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76
547 MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16
551 pinctrl_pcie1_reg: pcie1reggrp {
553 MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16
557 pinctrl_qspi: qspigrp {
559 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
560 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
561 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
562 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
563 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
564 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
568 pinctrl_reg_usdhc2: regusdhc2gpiogrp {
570 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
574 pinctrl_sai2: sai2grp {
576 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
577 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
578 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
579 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
580 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
584 pinctrl_sai3: sai3grp {
586 MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
587 MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
588 MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
589 MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
593 pinctrl_spdif1: spdif1grp {
595 MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
596 MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
600 pinctrl_uart1: uart1grp {
602 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
603 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
607 pinctrl_usdhc1: usdhc1grp {
609 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
610 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
611 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
612 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
613 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
614 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
615 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
616 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
617 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
618 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
619 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
620 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
624 pinctrl_usdhc1_100mhz: usdhc1-100grp {
626 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
627 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
628 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
629 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
630 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
631 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
632 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
633 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
634 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
635 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
636 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
637 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
641 pinctrl_usdhc1_200mhz: usdhc1-200grp {
643 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
644 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
645 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
646 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
647 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
648 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
649 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
650 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
651 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
652 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
653 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
654 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
658 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
660 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
664 pinctrl_usdhc2: usdhc2grp {
666 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
667 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
668 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
669 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
670 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
671 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
672 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
676 pinctrl_usdhc2_100mhz: usdhc2-100grp {
678 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
679 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
680 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
681 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
682 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
683 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
684 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
688 pinctrl_usdhc2_200mhz: usdhc2-200grp {
690 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
691 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
692 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
693 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
694 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
695 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
696 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
700 pinctrl_wdog: wdog1grp {
702 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
706 pinctrl_wifi_reset: wifiresetgrp {
708 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16