1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
12 model = "NXP i.MX8MQ EVK";
13 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
20 device_type = "memory";
21 reg = <0x00000000 0x40000000 0 0xc0000000>;
24 pcie0_refclk: pcie0-refclk {
25 compatible = "fixed-clock";
27 clock-frequency = <100000000>;
30 reg_usdhc2_vmmc: regulator-vsd-3v3 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_reg_usdhc2>;
33 compatible = "regulator-fixed";
34 regulator-name = "VSD_3V3";
35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>;
37 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
41 buck2_reg: regulator-buck2 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_buck2>;
44 compatible = "regulator-gpio";
45 regulator-name = "vdd_arm";
46 regulator-min-microvolt = <900000>;
47 regulator-max-microvolt = <1000000>;
48 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
54 #sound-dai-cells = <0>;
55 compatible = "wlf,wm8524";
56 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
60 compatible = "simple-audio-card";
61 simple-audio-card,name = "wm8524-audio";
62 simple-audio-card,format = "i2s";
63 simple-audio-card,frame-master = <&cpudai>;
64 simple-audio-card,bitclock-master = <&cpudai>;
65 simple-audio-card,widgets =
66 "Line", "Left Line Out Jack",
67 "Line", "Right Line Out Jack";
68 simple-audio-card,routing =
69 "Left Line Out Jack", "LINEVOUTL",
70 "Right Line Out Jack", "LINEVOUTR";
72 cpudai: simple-audio-card,cpu {
76 link_codec: simple-audio-card,codec {
77 sound-dai = <&wm8524>;
78 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
84 cpu-supply = <&buck2_reg>;
88 cpu-supply = <&buck2_reg>;
92 cpu-supply = <&buck2_reg>;
96 cpu-supply = <&buck2_reg>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_fec1>;
102 phy-mode = "rgmii-id";
103 phy-handle = <ðphy0>;
108 #address-cells = <1>;
111 ethphy0: ethernet-phy@0 {
112 compatible = "ethernet-phy-ieee802.3-c22";
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_sai2>;
121 assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
122 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
123 assigned-clock-rates = <0>, <24576000>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_wifi_reset>;
133 gpios = <29 GPIO_ACTIVE_HIGH>;
139 clock-frequency = <100000>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_i2c1>;
145 compatible = "fsl,pfuze100";
150 regulator-min-microvolt = <825000>;
151 regulator-max-microvolt = <1100000>;
155 regulator-min-microvolt = <825000>;
156 regulator-max-microvolt = <1100000>;
160 regulator-min-microvolt = <1100000>;
161 regulator-max-microvolt = <1100000>;
166 regulator-min-microvolt = <825000>;
167 regulator-max-microvolt = <1100000>;
172 regulator-min-microvolt = <1800000>;
173 regulator-max-microvolt = <1800000>;
178 regulator-min-microvolt = <5000000>;
179 regulator-max-microvolt = <5150000>;
183 regulator-min-microvolt = <1000000>;
184 regulator-max-microvolt = <3000000>;
193 regulator-min-microvolt = <800000>;
194 regulator-max-microvolt = <1550000>;
198 regulator-min-microvolt = <850000>;
199 regulator-max-microvolt = <975000>;
204 regulator-min-microvolt = <1675000>;
205 regulator-max-microvolt = <1975000>;
210 regulator-min-microvolt = <1625000>;
211 regulator-max-microvolt = <1875000>;
216 regulator-min-microvolt = <3075000>;
217 regulator-max-microvolt = <3625000>;
222 regulator-min-microvolt = <1800000>;
223 regulator-max-microvolt = <3300000>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_pcie0>;
232 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
233 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
234 <&clk IMX8MQ_CLK_PCIE1_AUX>,
235 <&clk IMX8MQ_CLK_PCIE1_PHY>,
237 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
242 power-supply = <&sw1a_reg>;
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_uart1>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_qspi>;
271 #address-cells = <1>;
273 compatible = "micron,n25q256a", "jedec,spi-nor";
274 spi-max-frequency = <29000000>;
279 pinctrl-names = "default", "state_100mhz", "state_200mhz";
280 pinctrl-0 = <&pinctrl_usdhc1>;
281 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
282 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
283 vqmmc-supply = <&sw4_reg>;
292 pinctrl-names = "default", "state_100mhz", "state_200mhz";
293 pinctrl-0 = <&pinctrl_usdhc2>;
294 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
295 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
296 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
297 vmmc-supply = <®_usdhc2_vmmc>;
302 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_wdog>;
304 fsl,ext-reset-output;
309 pinctrl_buck2: vddarmgrp {
311 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
316 pinctrl_fec1: fec1grp {
318 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
319 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
320 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
321 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
322 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
323 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
324 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
325 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
326 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
327 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
328 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
329 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
330 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
331 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
332 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
336 pinctrl_i2c1: i2c1grp {
338 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
339 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
343 pinctrl_pcie0: pcie0grp {
345 MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
346 MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
350 pinctrl_qspi: qspigrp {
352 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
353 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
354 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
355 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
356 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
357 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
362 pinctrl_reg_usdhc2: regusdhc2grpgpio {
364 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
368 pinctrl_sai2: sai2grp {
370 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
371 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
372 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
373 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
374 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
378 pinctrl_uart1: uart1grp {
380 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
381 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
385 pinctrl_usdhc1: usdhc1grp {
387 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
388 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
389 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
390 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
391 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
392 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
393 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
394 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
395 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
396 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
397 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
398 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
402 pinctrl_usdhc1_100mhz: usdhc1-100grp {
404 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
405 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
406 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
407 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
408 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
409 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
410 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
411 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
412 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
413 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
414 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
415 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
419 pinctrl_usdhc1_200mhz: usdhc1-200grp {
421 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
422 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
423 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
424 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
425 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
426 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
427 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
428 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
429 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
430 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
431 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
432 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
436 pinctrl_usdhc2: usdhc2grp {
438 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
439 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
440 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
441 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
442 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
443 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
444 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
448 pinctrl_usdhc2_100mhz: usdhc2-100grp {
450 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
451 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
452 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
453 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
454 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
455 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
456 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
460 pinctrl_usdhc2_200mhz: usdhc2-200grp {
462 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
463 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
464 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
465 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
466 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
467 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
468 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
472 pinctrl_wdog: wdog1grp {
474 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
478 pinctrl_wifi_reset: wifiresetgrp {
480 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16