1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
18 interrupt-parent = <&gic>;
52 compatible = "arm,cortex-a53";
54 clock-latency = <61036>;
55 clocks = <&clk IMX8MP_CLK_ARM>;
56 enable-method = "psci";
57 i-cache-size = <0x8000>;
58 i-cache-line-size = <64>;
60 d-cache-size = <0x8000>;
61 d-cache-line-size = <64>;
63 next-level-cache = <&A53_L2>;
64 nvmem-cells = <&cpu_speed_grade>;
65 nvmem-cell-names = "speed_grade";
66 operating-points-v2 = <&a53_opp_table>;
72 compatible = "arm,cortex-a53";
74 clock-latency = <61036>;
75 clocks = <&clk IMX8MP_CLK_ARM>;
76 enable-method = "psci";
77 i-cache-size = <0x8000>;
78 i-cache-line-size = <64>;
80 d-cache-size = <0x8000>;
81 d-cache-line-size = <64>;
83 next-level-cache = <&A53_L2>;
84 operating-points-v2 = <&a53_opp_table>;
90 compatible = "arm,cortex-a53";
92 clock-latency = <61036>;
93 clocks = <&clk IMX8MP_CLK_ARM>;
94 enable-method = "psci";
95 i-cache-size = <0x8000>;
96 i-cache-line-size = <64>;
98 d-cache-size = <0x8000>;
99 d-cache-line-size = <64>;
100 d-cache-sets = <128>;
101 next-level-cache = <&A53_L2>;
102 operating-points-v2 = <&a53_opp_table>;
103 #cooling-cells = <2>;
108 compatible = "arm,cortex-a53";
110 clock-latency = <61036>;
111 clocks = <&clk IMX8MP_CLK_ARM>;
112 enable-method = "psci";
113 i-cache-size = <0x8000>;
114 i-cache-line-size = <64>;
115 i-cache-sets = <256>;
116 d-cache-size = <0x8000>;
117 d-cache-line-size = <64>;
118 d-cache-sets = <128>;
119 next-level-cache = <&A53_L2>;
120 operating-points-v2 = <&a53_opp_table>;
121 #cooling-cells = <2>;
125 compatible = "cache";
127 cache-size = <0x80000>;
128 cache-line-size = <64>;
133 a53_opp_table: opp-table {
134 compatible = "operating-points-v2";
138 opp-hz = /bits/ 64 <1200000000>;
139 opp-microvolt = <850000>;
140 opp-supported-hw = <0x8a0>, <0x7>;
141 clock-latency-ns = <150000>;
146 opp-hz = /bits/ 64 <1600000000>;
147 opp-microvolt = <950000>;
148 opp-supported-hw = <0xa0>, <0x7>;
149 clock-latency-ns = <150000>;
154 opp-hz = /bits/ 64 <1800000000>;
155 opp-microvolt = <1000000>;
156 opp-supported-hw = <0x20>, <0x3>;
157 clock-latency-ns = <150000>;
162 osc_32k: clock-osc-32k {
163 compatible = "fixed-clock";
165 clock-frequency = <32768>;
166 clock-output-names = "osc_32k";
169 osc_24m: clock-osc-24m {
170 compatible = "fixed-clock";
172 clock-frequency = <24000000>;
173 clock-output-names = "osc_24m";
176 clk_ext1: clock-ext1 {
177 compatible = "fixed-clock";
179 clock-frequency = <133000000>;
180 clock-output-names = "clk_ext1";
183 clk_ext2: clock-ext2 {
184 compatible = "fixed-clock";
186 clock-frequency = <133000000>;
187 clock-output-names = "clk_ext2";
190 clk_ext3: clock-ext3 {
191 compatible = "fixed-clock";
193 clock-frequency = <133000000>;
194 clock-output-names = "clk_ext3";
197 clk_ext4: clock-ext4 {
198 compatible = "fixed-clock";
200 clock-frequency = <133000000>;
201 clock-output-names = "clk_ext4";
205 #address-cells = <2>;
209 dsp_reserved: dsp@92400000 {
210 reg = <0 0x92400000 0 0x2000000>;
216 compatible = "arm,cortex-a53-pmu";
217 interrupts = <GIC_PPI 7
218 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
222 compatible = "arm,psci-1.0";
228 polling-delay-passive = <250>;
229 polling-delay = <2000>;
230 thermal-sensors = <&tmu 0>;
233 temperature = <85000>;
239 temperature = <95000>;
247 trip = <&cpu_alert0>;
249 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
250 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
251 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
252 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
258 polling-delay-passive = <250>;
259 polling-delay = <2000>;
260 thermal-sensors = <&tmu 1>;
263 temperature = <85000>;
269 temperature = <95000>;
277 trip = <&soc_alert0>;
279 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
280 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
281 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
282 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
289 compatible = "arm,armv8-timer";
290 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
291 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
292 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
293 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
294 clock-frequency = <8000000>;
295 arm,no-tick-in-suspend;
299 compatible = "fsl,imx8mp-soc", "simple-bus";
300 #address-cells = <1>;
302 ranges = <0x0 0x0 0x0 0x3e000000>;
303 nvmem-cells = <&imx8mp_uid>;
304 nvmem-cell-names = "soc_unique_id";
306 aips1: bus@30000000 {
307 compatible = "fsl,aips-bus", "simple-bus";
308 reg = <0x30000000 0x400000>;
309 #address-cells = <1>;
313 gpio1: gpio@30200000 {
314 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
315 reg = <0x30200000 0x10000>;
316 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
321 interrupt-controller;
322 #interrupt-cells = <2>;
323 gpio-ranges = <&iomuxc 0 5 30>;
326 gpio2: gpio@30210000 {
327 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
328 reg = <0x30210000 0x10000>;
329 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
334 interrupt-controller;
335 #interrupt-cells = <2>;
336 gpio-ranges = <&iomuxc 0 35 21>;
339 gpio3: gpio@30220000 {
340 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
341 reg = <0x30220000 0x10000>;
342 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
349 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
352 gpio4: gpio@30230000 {
353 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
354 reg = <0x30230000 0x10000>;
355 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
360 interrupt-controller;
361 #interrupt-cells = <2>;
362 gpio-ranges = <&iomuxc 0 82 32>;
365 gpio5: gpio@30240000 {
366 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
367 reg = <0x30240000 0x10000>;
368 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
369 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
373 interrupt-controller;
374 #interrupt-cells = <2>;
375 gpio-ranges = <&iomuxc 0 114 30>;
379 compatible = "fsl,imx8mp-tmu";
380 reg = <0x30260000 0x10000>;
381 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
382 #thermal-sensor-cells = <1>;
385 wdog1: watchdog@30280000 {
386 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
387 reg = <0x30280000 0x10000>;
388 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
393 wdog2: watchdog@30290000 {
394 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
395 reg = <0x30290000 0x10000>;
396 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
401 wdog3: watchdog@302a0000 {
402 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
403 reg = <0x302a0000 0x10000>;
404 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
409 iomuxc: pinctrl@30330000 {
410 compatible = "fsl,imx8mp-iomuxc";
411 reg = <0x30330000 0x10000>;
414 gpr: iomuxc-gpr@30340000 {
415 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
416 reg = <0x30340000 0x10000>;
419 ocotp: efuse@30350000 {
420 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
421 reg = <0x30350000 0x10000>;
422 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
423 /* For nvmem subnodes */
424 #address-cells = <1>;
427 imx8mp_uid: unique-id@8 {
431 cpu_speed_grade: speed-grade@10 {
435 eth_mac1: mac-address@90 {
439 eth_mac2: mac-address@96 {
444 anatop: anatop@30360000 {
445 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
447 reg = <0x30360000 0x10000>;
450 snvs: snvs@30370000 {
451 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
452 reg = <0x30370000 0x10000>;
454 snvs_rtc: snvs-rtc-lp {
455 compatible = "fsl,sec-v4.0-mon-rtc-lp";
458 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
461 clock-names = "snvs-rtc";
464 snvs_pwrkey: snvs-powerkey {
465 compatible = "fsl,sec-v4.0-pwrkey";
467 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
469 clock-names = "snvs-pwrkey";
470 linux,keycode = <KEY_POWER>;
475 snvs_lpgpr: snvs-lpgpr {
476 compatible = "fsl,imx8mp-snvs-lpgpr",
477 "fsl,imx7d-snvs-lpgpr";
481 clk: clock-controller@30380000 {
482 compatible = "fsl,imx8mp-ccm";
483 reg = <0x30380000 0x10000>;
485 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
486 <&clk_ext3>, <&clk_ext4>;
487 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
488 "clk_ext3", "clk_ext4";
489 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
490 <&clk IMX8MP_CLK_A53_CORE>,
491 <&clk IMX8MP_CLK_NOC>,
492 <&clk IMX8MP_CLK_NOC_IO>,
493 <&clk IMX8MP_CLK_GIC>,
494 <&clk IMX8MP_CLK_AUDIO_AHB>,
495 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
496 <&clk IMX8MP_AUDIO_PLL1>,
497 <&clk IMX8MP_AUDIO_PLL2>;
498 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
499 <&clk IMX8MP_ARM_PLL_OUT>,
500 <&clk IMX8MP_SYS_PLL2_1000M>,
501 <&clk IMX8MP_SYS_PLL1_800M>,
502 <&clk IMX8MP_SYS_PLL2_500M>,
503 <&clk IMX8MP_SYS_PLL1_800M>,
504 <&clk IMX8MP_SYS_PLL1_800M>;
505 assigned-clock-rates = <0>, <0>,
515 src: reset-controller@30390000 {
516 compatible = "fsl,imx8mp-src", "syscon";
517 reg = <0x30390000 0x10000>;
518 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
523 compatible = "fsl,imx8mp-gpc";
524 reg = <0x303a0000 0x1000>;
525 interrupt-parent = <&gic>;
526 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
527 interrupt-controller;
528 #interrupt-cells = <3>;
531 #address-cells = <1>;
534 pgc_mipi_phy1: power-domain@0 {
535 #power-domain-cells = <0>;
536 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
539 pgc_pcie_phy: power-domain@1 {
540 #power-domain-cells = <0>;
541 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
544 pgc_usb1_phy: power-domain@2 {
545 #power-domain-cells = <0>;
546 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
549 pgc_usb2_phy: power-domain@3 {
550 #power-domain-cells = <0>;
551 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
554 pgc_gpu2d: power-domain@6 {
555 #power-domain-cells = <0>;
556 reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
557 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
558 power-domains = <&pgc_gpumix>;
561 pgc_gpumix: power-domain@7 {
562 #power-domain-cells = <0>;
563 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
564 clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
565 <&clk IMX8MP_CLK_GPU_AHB>;
566 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
567 <&clk IMX8MP_CLK_GPU_AHB>;
568 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
569 <&clk IMX8MP_SYS_PLL1_800M>;
570 assigned-clock-rates = <800000000>, <400000000>;
573 pgc_gpu3d: power-domain@9 {
574 #power-domain-cells = <0>;
575 reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
576 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
577 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
578 power-domains = <&pgc_gpumix>;
581 pgc_mediamix: power-domain@10 {
582 #power-domain-cells = <0>;
583 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
584 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
585 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
588 pgc_mipi_phy2: power-domain@16 {
589 #power-domain-cells = <0>;
590 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
593 pgc_hsiomix: power-domain@17 {
594 #power-domain-cells = <0>;
595 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
596 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
597 <&clk IMX8MP_CLK_HSIO_ROOT>;
598 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
599 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
600 assigned-clock-rates = <500000000>;
603 pgc_ispdwp: power-domain@18 {
604 #power-domain-cells = <0>;
605 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
606 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
609 pgc_vpumix: power-domain@19 {
610 #power-domain-cells = <0>;
611 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
612 clocks =<&clk IMX8MP_CLK_VPU_ROOT>;
615 pgc_vpu_g1: power-domain@20 {
616 #power-domain-cells = <0>;
617 power-domains = <&pgc_vpumix>;
618 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
619 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
622 pgc_vpu_g2: power-domain@21 {
623 #power-domain-cells = <0>;
624 power-domains = <&pgc_vpumix>;
625 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
626 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
629 pgc_vpu_vc8000e: power-domain@22 {
630 #power-domain-cells = <0>;
631 power-domains = <&pgc_vpumix>;
632 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
633 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
639 aips2: bus@30400000 {
640 compatible = "fsl,aips-bus", "simple-bus";
641 reg = <0x30400000 0x400000>;
642 #address-cells = <1>;
647 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
648 reg = <0x30660000 0x10000>;
649 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
650 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
651 <&clk IMX8MP_CLK_PWM1_ROOT>;
652 clock-names = "ipg", "per";
658 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
659 reg = <0x30670000 0x10000>;
660 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
662 <&clk IMX8MP_CLK_PWM2_ROOT>;
663 clock-names = "ipg", "per";
669 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
670 reg = <0x30680000 0x10000>;
671 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
673 <&clk IMX8MP_CLK_PWM3_ROOT>;
674 clock-names = "ipg", "per";
680 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
681 reg = <0x30690000 0x10000>;
682 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
684 <&clk IMX8MP_CLK_PWM4_ROOT>;
685 clock-names = "ipg", "per";
690 system_counter: timer@306a0000 {
691 compatible = "nxp,sysctr-timer";
692 reg = <0x306a0000 0x20000>;
693 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
699 aips3: bus@30800000 {
700 compatible = "fsl,aips-bus", "simple-bus";
701 reg = <0x30800000 0x400000>;
702 #address-cells = <1>;
706 ecspi1: spi@30820000 {
707 #address-cells = <1>;
709 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
710 reg = <0x30820000 0x10000>;
711 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
713 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
714 clock-names = "ipg", "per";
715 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
716 dma-names = "rx", "tx";
720 ecspi2: spi@30830000 {
721 #address-cells = <1>;
723 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
724 reg = <0x30830000 0x10000>;
725 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
727 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
728 clock-names = "ipg", "per";
729 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
730 dma-names = "rx", "tx";
734 ecspi3: spi@30840000 {
735 #address-cells = <1>;
737 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
738 reg = <0x30840000 0x10000>;
739 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
741 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
742 clock-names = "ipg", "per";
743 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
744 dma-names = "rx", "tx";
748 uart1: serial@30860000 {
749 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
750 reg = <0x30860000 0x10000>;
751 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
753 <&clk IMX8MP_CLK_UART1_ROOT>;
754 clock-names = "ipg", "per";
755 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
756 dma-names = "rx", "tx";
760 uart3: serial@30880000 {
761 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
762 reg = <0x30880000 0x10000>;
763 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
765 <&clk IMX8MP_CLK_UART3_ROOT>;
766 clock-names = "ipg", "per";
767 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
768 dma-names = "rx", "tx";
772 uart2: serial@30890000 {
773 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
774 reg = <0x30890000 0x10000>;
775 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
776 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
777 <&clk IMX8MP_CLK_UART2_ROOT>;
778 clock-names = "ipg", "per";
779 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
780 dma-names = "rx", "tx";
784 flexcan1: can@308c0000 {
785 compatible = "fsl,imx8mp-flexcan";
786 reg = <0x308c0000 0x10000>;
787 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
789 <&clk IMX8MP_CLK_CAN1_ROOT>;
790 clock-names = "ipg", "per";
791 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
792 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
793 assigned-clock-rates = <40000000>;
794 fsl,clk-source = /bits/ 8 <0>;
795 fsl,stop-mode = <&gpr 0x10 4>;
799 flexcan2: can@308d0000 {
800 compatible = "fsl,imx8mp-flexcan";
801 reg = <0x308d0000 0x10000>;
802 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
804 <&clk IMX8MP_CLK_CAN2_ROOT>;
805 clock-names = "ipg", "per";
806 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
807 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
808 assigned-clock-rates = <40000000>;
809 fsl,clk-source = /bits/ 8 <0>;
810 fsl,stop-mode = <&gpr 0x10 5>;
814 crypto: crypto@30900000 {
815 compatible = "fsl,sec-v4.0";
816 #address-cells = <1>;
818 reg = <0x30900000 0x40000>;
819 ranges = <0 0x30900000 0x40000>;
820 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&clk IMX8MP_CLK_AHB>,
822 <&clk IMX8MP_CLK_IPG_ROOT>;
823 clock-names = "aclk", "ipg";
826 compatible = "fsl,sec-v4.0-job-ring";
827 reg = <0x1000 0x1000>;
828 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
833 compatible = "fsl,sec-v4.0-job-ring";
834 reg = <0x2000 0x1000>;
835 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
839 compatible = "fsl,sec-v4.0-job-ring";
840 reg = <0x3000 0x1000>;
841 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
846 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
847 #address-cells = <1>;
849 reg = <0x30a20000 0x10000>;
850 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
856 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
857 #address-cells = <1>;
859 reg = <0x30a30000 0x10000>;
860 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
866 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
867 #address-cells = <1>;
869 reg = <0x30a40000 0x10000>;
870 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
876 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
877 #address-cells = <1>;
879 reg = <0x30a50000 0x10000>;
880 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
881 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
885 uart4: serial@30a60000 {
886 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
887 reg = <0x30a60000 0x10000>;
888 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
890 <&clk IMX8MP_CLK_UART4_ROOT>;
891 clock-names = "ipg", "per";
892 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
893 dma-names = "rx", "tx";
897 mu: mailbox@30aa0000 {
898 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
899 reg = <0x30aa0000 0x10000>;
900 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
901 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
905 mu2: mailbox@30e60000 {
906 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
907 reg = <0x30e60000 0x10000>;
908 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
914 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
915 #address-cells = <1>;
917 reg = <0x30ad0000 0x10000>;
918 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
919 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
924 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
925 #address-cells = <1>;
927 reg = <0x30ae0000 0x10000>;
928 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
933 usdhc1: mmc@30b40000 {
934 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
935 reg = <0x30b40000 0x10000>;
936 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
937 clocks = <&clk IMX8MP_CLK_DUMMY>,
938 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
939 <&clk IMX8MP_CLK_USDHC1_ROOT>;
940 clock-names = "ipg", "ahb", "per";
941 fsl,tuning-start-tap = <20>;
942 fsl,tuning-step = <2>;
947 usdhc2: mmc@30b50000 {
948 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
949 reg = <0x30b50000 0x10000>;
950 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
951 clocks = <&clk IMX8MP_CLK_DUMMY>,
952 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
953 <&clk IMX8MP_CLK_USDHC2_ROOT>;
954 clock-names = "ipg", "ahb", "per";
955 fsl,tuning-start-tap = <20>;
956 fsl,tuning-step = <2>;
961 usdhc3: mmc@30b60000 {
962 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
963 reg = <0x30b60000 0x10000>;
964 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
965 clocks = <&clk IMX8MP_CLK_DUMMY>,
966 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
967 <&clk IMX8MP_CLK_USDHC3_ROOT>;
968 clock-names = "ipg", "ahb", "per";
969 fsl,tuning-start-tap = <20>;
970 fsl,tuning-step = <2>;
975 flexspi: spi@30bb0000 {
976 compatible = "nxp,imx8mp-fspi";
977 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
978 reg-names = "fspi_base", "fspi_mmap";
979 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
981 <&clk IMX8MP_CLK_QSPI_ROOT>;
982 clock-names = "fspi_en", "fspi";
983 assigned-clock-rates = <80000000>;
984 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
985 #address-cells = <1>;
990 sdma1: dma-controller@30bd0000 {
991 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
992 reg = <0x30bd0000 0x10000>;
993 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
995 <&clk IMX8MP_CLK_AHB>;
996 clock-names = "ipg", "ahb";
998 fsl,sdma-ram-script-name = "/*(DEBLOBBED)*/";
1001 fec: ethernet@30be0000 {
1002 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1003 reg = <0x30be0000 0x10000>;
1004 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1005 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1006 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1007 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1008 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
1009 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
1010 <&clk IMX8MP_CLK_ENET_TIMER>,
1011 <&clk IMX8MP_CLK_ENET_REF>,
1012 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1013 clock-names = "ipg", "ahb", "ptp",
1014 "enet_clk_ref", "enet_out";
1015 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1016 <&clk IMX8MP_CLK_ENET_TIMER>,
1017 <&clk IMX8MP_CLK_ENET_REF>,
1018 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1019 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1020 <&clk IMX8MP_SYS_PLL2_100M>,
1021 <&clk IMX8MP_SYS_PLL2_125M>,
1022 <&clk IMX8MP_SYS_PLL2_50M>;
1023 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1024 fsl,num-tx-queues = <3>;
1025 fsl,num-rx-queues = <3>;
1026 nvmem-cells = <ð_mac1>;
1027 nvmem-cell-names = "mac-address";
1028 fsl,stop-mode = <&gpr 0x10 3>;
1029 status = "disabled";
1032 eqos: ethernet@30bf0000 {
1033 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1034 reg = <0x30bf0000 0x10000>;
1035 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1036 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1037 interrupt-names = "macirq", "eth_wake_irq";
1038 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
1039 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
1040 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1041 <&clk IMX8MP_CLK_ENET_QOS>;
1042 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1043 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1044 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1045 <&clk IMX8MP_CLK_ENET_QOS>;
1046 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1047 <&clk IMX8MP_SYS_PLL2_100M>,
1048 <&clk IMX8MP_SYS_PLL2_125M>;
1049 assigned-clock-rates = <0>, <100000000>, <125000000>;
1050 nvmem-cells = <ð_mac2>;
1051 nvmem-cell-names = "mac-address";
1052 intf_mode = <&gpr 0x4>;
1053 status = "disabled";
1057 noc: interconnect@32700000 {
1058 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1059 reg = <0x32700000 0x100000>;
1060 clocks = <&clk IMX8MP_CLK_NOC>;
1061 #interconnect-cells = <1>;
1062 operating-points-v2 = <&noc_opp_table>;
1064 noc_opp_table: opp-table {
1065 compatible = "operating-points-v2";
1068 opp-hz = /bits/ 64 <200000000>;
1072 opp-hz = /bits/ 64 <1000000000>;
1077 aips4: bus@32c00000 {
1078 compatible = "fsl,aips-bus", "simple-bus";
1079 reg = <0x32c00000 0x400000>;
1080 #address-cells = <1>;
1084 media_blk_ctrl: blk-ctrl@32ec0000 {
1085 compatible = "fsl,imx8mp-media-blk-ctrl",
1087 reg = <0x32ec0000 0x10000>;
1088 power-domains = <&pgc_mediamix>,
1098 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1099 "lcdif1", "isi", "mipi-csi2",
1100 "lcdif2", "isp", "dwe",
1103 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>,
1104 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>,
1105 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>,
1106 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>,
1107 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>,
1108 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>,
1109 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>,
1110 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>;
1111 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
1112 "isi1", "isi2", "isp0", "isp1",
1114 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1115 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1116 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1117 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1118 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1119 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1120 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1121 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
1122 clock-names = "apb", "axi", "cam1", "cam2",
1123 "disp1", "disp2", "isp", "phy";
1125 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1126 <&clk IMX8MP_CLK_MEDIA_APB>;
1127 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1128 <&clk IMX8MP_SYS_PLL1_800M>;
1129 assigned-clock-rates = <500000000>, <200000000>;
1131 #power-domain-cells = <1>;
1134 pcie_phy: pcie-phy@32f00000 {
1135 compatible = "fsl,imx8mp-pcie-phy";
1136 reg = <0x32f00000 0x10000>;
1137 resets = <&src IMX8MP_RESET_PCIEPHY>,
1138 <&src IMX8MP_RESET_PCIEPHY_PERST>;
1139 reset-names = "pciephy", "perst";
1140 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
1142 status = "disabled";
1145 hsio_blk_ctrl: blk-ctrl@32f10000 {
1146 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
1147 reg = <0x32f10000 0x24>;
1148 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1149 <&clk IMX8MP_CLK_PCIE_ROOT>;
1150 clock-names = "usb", "pcie";
1151 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
1152 <&pgc_usb1_phy>, <&pgc_usb2_phy>,
1153 <&pgc_hsiomix>, <&pgc_pcie_phy>;
1154 power-domain-names = "bus", "usb", "usb-phy1",
1155 "usb-phy2", "pcie", "pcie-phy";
1156 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>,
1157 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>,
1158 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>,
1159 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>;
1160 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
1161 #power-domain-cells = <1>;
1165 pcie: pcie@33800000 {
1166 compatible = "fsl,imx8mp-pcie";
1167 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
1168 reg-names = "dbi", "config";
1169 #address-cells = <3>;
1171 device_type = "pci";
1172 bus-range = <0x00 0xff>;
1173 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1174 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1177 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1178 interrupt-names = "msi";
1179 #interrupt-cells = <1>;
1180 interrupt-map-mask = <0 0 0 0x7>;
1181 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1182 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1183 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1184 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1185 fsl,max-link-speed = <3>;
1186 linux,pci-domain = <0>;
1187 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
1188 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
1189 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
1190 reset-names = "apps", "turnoff";
1192 phy-names = "pcie-phy";
1193 status = "disabled";
1196 gpu3d: gpu@38000000 {
1197 compatible = "vivante,gc";
1198 reg = <0x38000000 0x8000>;
1199 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1200 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
1201 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
1202 <&clk IMX8MP_CLK_GPU_ROOT>,
1203 <&clk IMX8MP_CLK_GPU_AHB>;
1204 clock-names = "core", "shader", "bus", "reg";
1205 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
1206 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
1207 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1208 <&clk IMX8MP_SYS_PLL1_800M>;
1209 assigned-clock-rates = <800000000>, <800000000>;
1210 power-domains = <&pgc_gpu3d>;
1213 gpu2d: gpu@38008000 {
1214 compatible = "vivante,gc";
1215 reg = <0x38008000 0x8000>;
1216 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1217 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
1218 <&clk IMX8MP_CLK_GPU_ROOT>,
1219 <&clk IMX8MP_CLK_GPU_AHB>;
1220 clock-names = "core", "bus", "reg";
1221 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
1222 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1223 assigned-clock-rates = <800000000>;
1224 power-domains = <&pgc_gpu2d>;
1227 vpumix_blk_ctrl: blk-ctrl@38330000 {
1228 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
1229 reg = <0x38330000 0x100>;
1230 #power-domain-cells = <1>;
1231 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1232 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>;
1233 power-domain-names = "bus", "g1", "g2", "vc8000e";
1234 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>,
1235 <&clk IMX8MP_CLK_VPU_G2_ROOT>,
1236 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
1237 clock-names = "g1", "g2", "vc8000e";
1238 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>,
1239 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>,
1240 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;
1241 interconnect-names = "g1", "g2", "vc8000e";
1244 gic: interrupt-controller@38800000 {
1245 compatible = "arm,gic-v3";
1246 reg = <0x38800000 0x10000>,
1247 <0x38880000 0xc0000>;
1248 #interrupt-cells = <3>;
1249 interrupt-controller;
1250 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1251 interrupt-parent = <&gic>;
1254 edacmc: memory-controller@3d400000 {
1255 compatible = "snps,ddrc-3.80a";
1256 reg = <0x3d400000 0x400000>;
1257 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1261 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
1262 reg = <0x3d800000 0x400000>;
1263 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1266 usb3_phy0: usb-phy@381f0040 {
1267 compatible = "fsl,imx8mp-usb-phy";
1268 reg = <0x381f0040 0x40>;
1269 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1270 clock-names = "phy";
1271 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1272 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
1273 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
1275 status = "disabled";
1278 usb3_0: usb@32f10100 {
1279 compatible = "fsl,imx8mp-dwc3";
1280 reg = <0x32f10100 0x8>,
1282 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1283 <&clk IMX8MP_CLK_USB_SUSP>;
1284 clock-names = "hsio", "suspend";
1285 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1286 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
1287 #address-cells = <1>;
1289 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1291 status = "disabled";
1293 usb_dwc3_0: usb@38100000 {
1294 compatible = "snps,dwc3";
1295 reg = <0x38100000 0x10000>;
1296 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1297 <&clk IMX8MP_CLK_USB_CORE_REF>,
1298 <&clk IMX8MP_CLK_USB_SUSP>;
1299 clock-names = "bus_early", "ref", "suspend";
1300 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1301 phys = <&usb3_phy0>, <&usb3_phy0>;
1302 phy-names = "usb2-phy", "usb3-phy";
1303 snps,gfladj-refclk-lpm-sel-quirk;
1304 snps,parkmode-disable-ss-quirk;
1309 usb3_phy1: usb-phy@382f0040 {
1310 compatible = "fsl,imx8mp-usb-phy";
1311 reg = <0x382f0040 0x40>;
1312 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1313 clock-names = "phy";
1314 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1315 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
1316 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
1318 status = "disabled";
1321 usb3_1: usb@32f10108 {
1322 compatible = "fsl,imx8mp-dwc3";
1323 reg = <0x32f10108 0x8>,
1325 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1326 <&clk IMX8MP_CLK_USB_SUSP>;
1327 clock-names = "hsio", "suspend";
1328 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
1329 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
1330 #address-cells = <1>;
1332 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
1334 status = "disabled";
1336 usb_dwc3_1: usb@38200000 {
1337 compatible = "snps,dwc3";
1338 reg = <0x38200000 0x10000>;
1339 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1340 <&clk IMX8MP_CLK_USB_CORE_REF>,
1341 <&clk IMX8MP_CLK_USB_SUSP>;
1342 clock-names = "bus_early", "ref", "suspend";
1343 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1344 phys = <&usb3_phy1>, <&usb3_phy1>;
1345 phy-names = "usb2-phy", "usb3-phy";
1346 snps,gfladj-refclk-lpm-sel-quirk;
1347 snps,parkmode-disable-ss-quirk;
1352 compatible = "fsl,imx8mp-dsp";
1353 reg = <0x3b6e8000 0x88000>;
1354 mbox-names = "txdb0", "txdb1",
1356 mboxes = <&mu2 2 0>, <&mu2 2 1>,
1357 <&mu2 3 0>, <&mu2 3 1>;
1358 memory-region = <&dsp_reserved>;
1359 status = "disabled";