arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /*
   3  * Copyright 2022 Toradex
   4  */
   5
   6 #include <dt-bindings/phy/phy-imx8-pcie.h>
   7 #include <dt-bindings/pwm/pwm.h>
   8 #include "imx8mp.dtsi"
   9
  10 / {
  11         chosen {
  12                 stdout-path = &uart3;
  13         };
  14
  15         aliases {
  16                 /* Ethernet aliases to ensure correct MAC addresses */
  17                 ethernet0 = &eqos;
  18                 ethernet1 = &fec;
  19                 rtc0 = &rtc_i2c;
  20                 rtc1 = &snvs_rtc;
  21         };
  22
  23         backlight: backlight {
  24                 compatible = "pwm-backlight";
  25                 brightness-levels = <0 45 63 88 119 158 203 255>;
  26                 default-brightness-level = <4>;
  27                 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
  28                 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
  29                 pinctrl-names = "default";
  30                 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
  31                 power-supply = <&reg_3p3v>;
  32                 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
  33                 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>;
  34                 status = "disabled";
  35         };
  36
  37         backlight_mezzanine: backlight-mezzanine {
  38                 compatible = "pwm-backlight";
  39                 brightness-levels = <0 45 63 88 119 158 203 255>;
  40                 default-brightness-level = <4>;
  41                 /* Verdin GPIO 4 (SODIMM 212) */
  42                 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
  43                 /* Verdin PWM_2 (SODIMM 16) */
  44                 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>;
  45                 status = "disabled";
  46         };
  47
  48         gpio-keys {
  49                 compatible = "gpio-keys";
  50                 pinctrl-names = "default";
  51                 pinctrl-0 = <&pinctrl_gpio_keys>;
  52
  53                 key-wakeup {
  54                         debounce-interval = <10>;
  55                         /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
  56                         gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
  57                         label = "Wake-Up";
  58                         linux,code = <KEY_WAKEUP>;
  59                         wakeup-source;
  60                 };
  61         };
  62
  63         /* Carrier Board Supplies */
  64         reg_1p8v: regulator-1p8v {
  65                 compatible = "regulator-fixed";
  66                 regulator-max-microvolt = <1800000>;
  67                 regulator-min-microvolt = <1800000>;
  68                 regulator-name = "+V1.8_SW";
  69         };
  70
  71         reg_3p3v: regulator-3p3v {
  72                 compatible = "regulator-fixed";
  73                 regulator-max-microvolt = <3300000>;
  74                 regulator-min-microvolt = <3300000>;
  75                 regulator-name = "+V3.3_SW";
  76         };
  77
  78         reg_5p0v: regulator-5p0v {
  79                 compatible = "regulator-fixed";
  80                 regulator-max-microvolt = <5000000>;
  81                 regulator-min-microvolt = <5000000>;
  82                 regulator-name = "+V5_SW";
  83         };
  84
  85         /* Non PMIC On-module Supplies */
  86         reg_module_eth1phy: regulator-module-eth1phy {
  87                 compatible = "regulator-fixed";
  88                 enable-active-high;
  89                 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
  90                 off-on-delay-us = <500000>;
  91                 pinctrl-names = "default";
  92                 pinctrl-0 = <&pinctrl_reg_eth>;
  93                 regulator-always-on;
  94                 regulator-boot-on;
  95                 regulator-max-microvolt = <3300000>;
  96                 regulator-min-microvolt = <3300000>;
  97                 regulator-name = "On-module +V3.3_ETH";
  98                 startup-delay-us = <200000>;
  99                 vin-supply = <&reg_vdd_3v3>;
 100         };
 101
 102         reg_usb1_vbus: regulator-usb1-vbus {
 103                 compatible = "regulator-fixed";
 104                 enable-active-high;
 105                 /* Verdin USB_1_EN (SODIMM 155) */
 106                 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 107                 pinctrl-names = "default";
 108                 pinctrl-0 = <&pinctrl_usb1_vbus>;
 109                 regulator-max-microvolt = <5000000>;
 110                 regulator-min-microvolt = <5000000>;
 111                 regulator-name = "USB_1_EN";
 112         };
 113
 114         reg_usb2_vbus: regulator-usb2-vbus {
 115                 compatible = "regulator-fixed";
 116                 enable-active-high;
 117                 /* Verdin USB_2_EN (SODIMM 185) */
 118                 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
 119                 pinctrl-names = "default";
 120                 pinctrl-0 = <&pinctrl_usb2_vbus>;
 121                 regulator-max-microvolt = <5000000>;
 122                 regulator-min-microvolt = <5000000>;
 123                 regulator-name = "USB_2_EN";
 124         };
 125
 126         reg_usdhc2_vmmc: regulator-usdhc2 {
 127                 compatible = "regulator-fixed";
 128                 enable-active-high;
 129                 /* Verdin SD_1_PWR_EN (SODIMM 76) */
 130                 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
 131                 off-on-delay-us = <100000>;
 132                 pinctrl-names = "default";
 133                 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
 134                 regulator-max-microvolt = <3300000>;
 135                 regulator-min-microvolt = <3300000>;
 136                 regulator-name = "+V3.3_SD";
 137                 startup-delay-us = <2000>;
 138         };
 139
 140         reserved-memory {
 141                 #address-cells = <2>;
 142                 #size-cells = <2>;
 143                 ranges;
 144
 145                 /* Use the kernel configuration settings instead */
 146                 /delete-node/ linux,cma;
 147         };
 148 };
 149
 150 &A53_0 {
 151         cpu-supply = <&reg_vdd_arm>;
 152 };
 153
 154 &A53_1 {
 155         cpu-supply = <&reg_vdd_arm>;
 156 };
 157
 158 &A53_2 {
 159         cpu-supply = <&reg_vdd_arm>;
 160 };
 161
 162 &A53_3 {
 163         cpu-supply = <&reg_vdd_arm>;
 164 };
 165
 166 &cpu_alert0 {
 167         temperature = <95000>;
 168 };
 169
 170 &cpu_crit0 {
 171         temperature = <105000>;
 172 };
 173
 174 /* Verdin SPI_1 */
 175 &ecspi1 {
 176         #address-cells = <1>;
 177         #size-cells = <0>;
 178         cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 179         pinctrl-names = "default";
 180         pinctrl-0 = <&pinctrl_ecspi1>;
 181 };
 182
 183 /* Verdin ETH_1 (On-module PHY) */
 184 &eqos {
 185         phy-handle = <&ethphy0>;
 186         phy-mode = "rgmii-id";
 187         pinctrl-names = "default";
 188         pinctrl-0 = <&pinctrl_eqos>;
 189         snps,force_thresh_dma_mode;
 190         snps,mtl-rx-config = <&mtl_rx_setup>;
 191         snps,mtl-tx-config = <&mtl_tx_setup>;
 192
 193         mdio {
 194                 compatible = "snps,dwmac-mdio";
 195                 #address-cells = <1>;
 196                 #size-cells = <0>;
 197
 198                 ethphy0: ethernet-phy@7 {
 199                         compatible = "ethernet-phy-ieee802.3-c22";
 200                         eee-broken-100tx;
 201                         eee-broken-1000t;
 202                         interrupt-parent = <&gpio1>;
 203                         interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
 204                         micrel,led-mode = <0>;
 205                         reg = <7>;
 206                 };
 207         };
 208
 209         mtl_rx_setup: rx-queues-config {
 210                 snps,rx-queues-to-use = <5>;
 211                 snps,rx-sched-sp;
 212
 213                 queue0 {
 214                         snps,dcb-algorithm;
 215                         snps,priority = <0x1>;
 216                         snps,map-to-dma-channel = <0>;
 217                 };
 218
 219                 queue1 {
 220                         snps,dcb-algorithm;
 221                         snps,priority = <0x2>;
 222                         snps,map-to-dma-channel = <1>;
 223                 };
 224
 225                 queue2 {
 226                         snps,dcb-algorithm;
 227                         snps,priority = <0x4>;
 228                         snps,map-to-dma-channel = <2>;
 229                 };
 230
 231                 queue3 {
 232                         snps,dcb-algorithm;
 233                         snps,priority = <0x8>;
 234                         snps,map-to-dma-channel = <3>;
 235                 };
 236
 237                 queue4 {
 238                         snps,dcb-algorithm;
 239                         snps,priority = <0xf0>;
 240                         snps,map-to-dma-channel = <4>;
 241                 };
 242         };
 243
 244         mtl_tx_setup: tx-queues-config {
 245                 snps,tx-queues-to-use = <5>;
 246                 snps,tx-sched-sp;
 247
 248                 queue0 {
 249                         snps,dcb-algorithm;
 250                         snps,priority = <0x1>;
 251                 };
 252
 253                 queue1 {
 254                         snps,dcb-algorithm;
 255                         snps,priority = <0x2>;
 256                 };
 257
 258                 queue2 {
 259                         snps,dcb-algorithm;
 260                         snps,priority = <0x4>;
 261                 };
 262
 263                 queue3 {
 264                         snps,dcb-algorithm;
 265                         snps,priority = <0x8>;
 266                 };
 267
 268                 queue4 {
 269                         snps,dcb-algorithm;
 270                         snps,priority = <0xf0>;
 271                 };
 272         };
 273 };
 274
 275 /* Verdin ETH_2_RGMII */
 276 &fec {
 277         fsl,magic-packet;
 278         phy-handle = <&ethphy1>;
 279         phy-mode = "rgmii-id";
 280         pinctrl-names = "default", "sleep";
 281         pinctrl-0 = <&pinctrl_fec>;
 282         pinctrl-1 = <&pinctrl_fec_sleep>;
 283
 284         mdio {
 285                 #address-cells = <1>;
 286                 #size-cells = <0>;
 287
 288                 ethphy1: ethernet-phy@7 {
 289                         compatible = "ethernet-phy-ieee802.3-c22";
 290                         interrupt-parent = <&gpio4>;
 291                         interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
 292                         micrel,led-mode = <0>;
 293                         reg = <7>;
 294                 };
 295         };
 296 };
 297
 298 /* Verdin CAN_1 */
 299 &flexcan1 {
 300         pinctrl-names = "default";
 301         pinctrl-0 = <&pinctrl_flexcan1>;
 302         status = "disabled";
 303 };
 304
 305 /* Verdin CAN_2 */
 306 &flexcan2 {
 307         pinctrl-names = "default";
 308         pinctrl-0 = <&pinctrl_flexcan2>;
 309         status = "disabled";
 310 };
 311
 312 /* Verdin QSPI_1 */
 313 &flexspi {
 314         pinctrl-names = "default";
 315         pinctrl-0 = <&pinctrl_flexspi0>;
 316 };
 317
 318 &gpio1 {
 319         gpio-line-names = "SODIMM_206",
 320                           "SODIMM_208",
 321                           "",
 322                           "",
 323                           "",
 324                           "SODIMM_210",
 325                           "SODIMM_212",
 326                           "SODIMM_216",
 327                           "SODIMM_218",
 328                           "",
 329                           "",
 330                           "SODIMM_16",
 331                           "SODIMM_155",
 332                           "SODIMM_157",
 333                           "SODIMM_185",
 334                           "SODIMM_91";
 335 };
 336
 337 &gpio2 {
 338         gpio-line-names = "",
 339                           "",
 340                           "",
 341                           "",
 342                           "",
 343                           "",
 344                           "SODIMM_143",
 345                           "SODIMM_141",
 346                           "",
 347                           "",
 348                           "SODIMM_161",
 349                           "",
 350                           "SODIMM_84",
 351                           "SODIMM_78",
 352                           "SODIMM_74",
 353                           "SODIMM_80",
 354                           "SODIMM_82",
 355                           "SODIMM_70",
 356                           "SODIMM_72";
 357 };
 358
 359 &gpio3 {
 360         gpio-line-names = "SODIMM_52",
 361                           "SODIMM_54",
 362                           "",
 363                           "",
 364                           "",
 365                           "",
 366                           "SODIMM_56",
 367                           "SODIMM_58",
 368                           "SODIMM_60",
 369                           "SODIMM_62",
 370                           "",
 371                           "",
 372                           "",
 373                           "",
 374                           "SODIMM_66",
 375                           "",
 376                           "SODIMM_64",
 377                           "",
 378                           "",
 379                           "SODIMM_34",
 380                           "SODIMM_19",
 381                           "",
 382                           "SODIMM_32",
 383                           "",
 384                           "",
 385                           "SODIMM_30",
 386                           "SODIMM_59",
 387                           "SODIMM_57",
 388                           "SODIMM_63",
 389                           "SODIMM_61";
 390 };
 391
 392 &gpio4 {
 393         gpio-line-names = "SODIMM_252",
 394                           "SODIMM_222",
 395                           "SODIMM_36",
 396                           "SODIMM_220",
 397                           "SODIMM_193",
 398                           "SODIMM_191",
 399                           "SODIMM_201",
 400                           "SODIMM_203",
 401                           "SODIMM_205",
 402                           "SODIMM_207",
 403                           "SODIMM_199",
 404                           "SODIMM_197",
 405                           "SODIMM_221",
 406                           "SODIMM_219",
 407                           "SODIMM_217",
 408                           "SODIMM_215",
 409                           "SODIMM_211",
 410                           "SODIMM_213",
 411                           "SODIMM_189",
 412                           "SODIMM_244",
 413                           "SODIMM_38",
 414                           "",
 415                           "SODIMM_76",
 416                           "SODIMM_135",
 417                           "SODIMM_133",
 418                           "SODIMM_17",
 419                           "SODIMM_24",
 420                           "SODIMM_26",
 421                           "SODIMM_21",
 422                           "SODIMM_256",
 423                           "SODIMM_48",
 424                           "SODIMM_44";
 425
 426         ctrl-sleep-moci-hog {
 427                 gpio-hog;
 428                 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
 429                 gpios = <29 GPIO_ACTIVE_HIGH>;
 430                 line-name = "CTRL_SLEEP_MOCI#";
 431                 output-high;
 432                 pinctrl-names = "default";
 433                 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
 434         };
 435 };
 436
 437 /* On-module I2C */
 438 &i2c1 {
 439         clock-frequency = <400000>;
 440         pinctrl-names = "default", "gpio";
 441         pinctrl-0 = <&pinctrl_i2c1>;
 442         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 443         scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 444         sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 445         status = "okay";
 446
 447         pca9450: pmic@25 {
 448                 compatible = "nxp,pca9450c";
 449                 interrupt-parent = <&gpio1>;
 450                 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
 451                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 452                 pinctrl-names = "default";
 453                 pinctrl-0 = <&pinctrl_pmic>;
 454                 reg = <0x25>;
 455
 456                 /*
 457                  * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the
 458                  * I2C level shifter for the TLA2024 ADC behind this PMIC.
 459                  */
 460
 461                 regulators {
 462                         BUCK1 {
 463                                 regulator-always-on;
 464                                 regulator-boot-on;
 465                                 regulator-max-microvolt = <1000000>;
 466                                 regulator-min-microvolt = <720000>;
 467                                 regulator-name = "On-module +VDD_SOC (BUCK1)";
 468                                 regulator-ramp-delay = <3125>;
 469                         };
 470
 471                         reg_vdd_arm: BUCK2 {
 472                                 nxp,dvs-run-voltage = <950000>;
 473                                 nxp,dvs-standby-voltage = <850000>;
 474                                 regulator-always-on;
 475                                 regulator-boot-on;
 476                                 regulator-max-microvolt = <1025000>;
 477                                 regulator-min-microvolt = <720000>;
 478                                 regulator-name = "On-module +VDD_ARM (BUCK2)";
 479                                 regulator-ramp-delay = <3125>;
 480                         };
 481
 482                         reg_vdd_3v3: BUCK4 {
 483                                 regulator-always-on;
 484                                 regulator-boot-on;
 485                                 regulator-max-microvolt = <3300000>;
 486                                 regulator-min-microvolt = <3300000>;
 487                                 regulator-name = "On-module +V3.3 (BUCK4)";
 488                         };
 489
 490                         reg_vdd_1v8: BUCK5 {
 491                                 regulator-always-on;
 492                                 regulator-boot-on;
 493                                 regulator-max-microvolt = <1800000>;
 494                                 regulator-min-microvolt = <1800000>;
 495                                 regulator-name = "PWR_1V8_MOCI (BUCK5)";
 496                         };
 497
 498                         BUCK6 {
 499                                 regulator-always-on;
 500                                 regulator-boot-on;
 501                                 regulator-max-microvolt = <1155000>;
 502                                 regulator-min-microvolt = <1045000>;
 503                                 regulator-name = "On-module +VDD_DDR (BUCK6)";
 504                         };
 505
 506                         LDO1 {
 507                                 regulator-always-on;
 508                                 regulator-boot-on;
 509                                 regulator-max-microvolt = <1950000>;
 510                                 regulator-min-microvolt = <1650000>;
 511                                 regulator-name = "On-module +V1.8_SNVS (LDO1)";
 512                         };
 513
 514                         LDO2 {
 515                                 regulator-always-on;
 516                                 regulator-boot-on;
 517                                 regulator-max-microvolt = <1150000>;
 518                                 regulator-min-microvolt = <800000>;
 519                                 regulator-name = "On-module +V0.8_SNVS (LDO2)";
 520                         };
 521
 522                         LDO3 {
 523                                 regulator-always-on;
 524                                 regulator-boot-on;
 525                                 regulator-max-microvolt = <1800000>;
 526                                 regulator-min-microvolt = <1800000>;
 527                                 regulator-name = "On-module +V1.8A (LDO3)";
 528                         };
 529
 530                         LDO4 {
 531                                 regulator-always-on;
 532                                 regulator-boot-on;
 533                                 regulator-max-microvolt = <3300000>;
 534                                 regulator-min-microvolt = <3300000>;
 535                                 regulator-name = "On-module +V3.3_ADC (LDO4)";
 536                         };
 537
 538                         LDO5 {
 539                                 regulator-max-microvolt = <3300000>;
 540                                 regulator-min-microvolt = <1800000>;
 541                                 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
 542                         };
 543                 };
 544         };
 545
 546         rtc_i2c: rtc@32 {
 547                 compatible = "epson,rx8130";
 548                 reg = <0x32>;
 549         };
 550
 551         /* On-module temperature sensor */
 552         hwmon_temp_module: sensor@48 {
 553                 compatible = "ti,tmp1075";
 554                 reg = <0x48>;
 555                 vs-supply = <&reg_vdd_1v8>;
 556         };
 557
 558         adc@49 {
 559                 compatible = "ti,ads1015";
 560                 reg = <0x49>;
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563
 564                 /* Verdin I2C_1 (ADC_4 - ADC_3) */
 565                 channel@0 {
 566                         reg = <0>;
 567                         ti,datarate = <4>;
 568                         ti,gain = <2>;
 569                 };
 570
 571                 /* Verdin I2C_1 (ADC_4 - ADC_1) */
 572                 channel@1 {
 573                         reg = <1>;
 574                         ti,datarate = <4>;
 575                         ti,gain = <2>;
 576                 };
 577
 578                 /* Verdin I2C_1 (ADC_3 - ADC_1) */
 579                 channel@2 {
 580                         reg = <2>;
 581                         ti,datarate = <4>;
 582                         ti,gain = <2>;
 583                 };
 584
 585                 /* Verdin I2C_1 (ADC_2 - ADC_1) */
 586                 channel@3 {
 587                         reg = <3>;
 588                         ti,datarate = <4>;
 589                         ti,gain = <2>;
 590                 };
 591
 592                 /* Verdin I2C_1 ADC_4 */
 593                 channel@4 {
 594                         reg = <4>;
 595                         ti,datarate = <4>;
 596                         ti,gain = <2>;
 597                 };
 598
 599                 /* Verdin I2C_1 ADC_3 */
 600                 channel@5 {
 601                         reg = <5>;
 602                         ti,datarate = <4>;
 603                         ti,gain = <2>;
 604                 };
 605
 606                 /* Verdin I2C_1 ADC_2 */
 607                 channel@6 {
 608                         reg = <6>;
 609                         ti,datarate = <4>;
 610                         ti,gain = <2>;
 611                 };
 612
 613                 /* Verdin I2C_1 ADC_1 */
 614                 channel@7 {
 615                         reg = <7>;
 616                         ti,datarate = <4>;
 617                         ti,gain = <2>;
 618                 };
 619         };
 620
 621         eeprom@50 {
 622                 compatible = "st,24c02";
 623                 pagesize = <16>;
 624                 reg = <0x50>;
 625         };
 626 };
 627
 628 /* Verdin I2C_2_DSI */
 629 &i2c2 {
 630         /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */
 631         clock-frequency = <10000>;
 632         pinctrl-names = "default", "gpio";
 633         pinctrl-0 = <&pinctrl_i2c2>;
 634         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 635         scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 636         sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 637
 638         atmel_mxt_ts_mezzanine: touch-mezzanine@4a {
 639                 compatible = "atmel,maxtouch";
 640                 /* Verdin GPIO_3 (SODIMM 210) */
 641                 interrupt-parent = <&gpio1>;
 642                 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
 643                 reg = <0x4a>;
 644                 /* Verdin GPIO_2 (SODIMM 208) */
 645                 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 646                 status = "disabled";
 647         };
 648 };
 649
 650 /* TODO: Verdin I2C_3_HDMI */
 651
 652 /* Verdin I2C_4_CSI */
 653 &i2c3 {
 654         clock-frequency = <400000>;
 655         pinctrl-names = "default", "gpio";
 656         pinctrl-0 = <&pinctrl_i2c3>;
 657         pinctrl-1 = <&pinctrl_i2c3_gpio>;
 658         scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 659         sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 660 };
 661
 662 /* Verdin I2C_1 */
 663 &i2c4 {
 664         clock-frequency = <400000>;
 665         pinctrl-names = "default", "gpio";
 666         pinctrl-0 = <&pinctrl_i2c4>;
 667         pinctrl-1 = <&pinctrl_i2c4_gpio>;
 668         scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 669         sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 670
 671         gpio_expander_21: gpio-expander@21 {
 672                 compatible = "nxp,pcal6416";
 673                 #gpio-cells = <2>;
 674                 gpio-controller;
 675                 reg = <0x21>;
 676                 vcc-supply = <&reg_3p3v>;
 677                 status = "disabled";
 678         };
 679
 680         lvds_ti_sn65dsi84: bridge@2c {
 681                 compatible = "ti,sn65dsi84";
 682                 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
 683                 /* Verdin GPIO_10_DSI (SODIMM 21) */
 684                 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
 685                 pinctrl-names = "default";
 686                 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
 687                 reg = <0x2c>;
 688                 status = "disabled";
 689         };
 690
 691         /* Current measurement into module VCC */
 692         hwmon: hwmon@40 {
 693                 compatible = "ti,ina219";
 694                 reg = <0x40>;
 695                 shunt-resistor = <10000>;
 696                 status = "disabled";
 697         };
 698
 699         hdmi_lontium_lt8912: hdmi@48 {
 700                 compatible = "lontium,lt8912b";
 701                 pinctrl-names = "default";
 702                 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
 703                 reg = <0x48>;
 704                 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
 705                 /* Verdin GPIO_10_DSI (SODIMM 21) */
 706                 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
 707                 status = "disabled";
 708         };
 709
 710         atmel_mxt_ts: touch@4a {
 711                 compatible = "atmel,maxtouch";
 712                 /*
 713                  * Verdin GPIO_9_DSI
 714                  * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
 715                  */
 716                 interrupt-parent = <&gpio4>;
 717                 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
 718                 pinctrl-names = "default";
 719                 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
 720                 reg = <0x4a>;
 721                 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
 722                 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 723                 status = "disabled";
 724         };
 725
 726         /* Temperature sensor on carrier board */
 727         hwmon_temp: sensor@4f {
 728                 compatible = "ti,tmp75c";
 729                 reg = <0x4f>;
 730                 status = "disabled";
 731         };
 732
 733         /* EEPROM on display adapter (MIPI DSI Display Adapter) */
 734         eeprom_display_adapter: eeprom@50 {
 735                 compatible = "st,24c02";
 736                 pagesize = <16>;
 737                 reg = <0x50>;
 738                 status = "disabled";
 739         };
 740
 741         /* EEPROM on carrier board */
 742         eeprom_carrier_board: eeprom@57 {
 743                 compatible = "st,24c02";
 744                 pagesize = <16>;
 745                 reg = <0x57>;
 746                 status = "disabled";
 747         };
 748 };
 749
 750 /* Verdin PCIE_1 */
 751 &pcie {
 752         pinctrl-names = "default";
 753         pinctrl-0 = <&pinctrl_pcie>;
 754         /* PCIE_1_RESET# (SODIMM 244) */
 755         reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
 756 };
 757
 758 &pcie_phy {
 759         clocks = <&hsio_blk_ctrl>;
 760         clock-names = "ref";
 761         fsl,clkreq-unsupported;
 762         fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
 763 };
 764
 765 /* Verdin PWM_1 */
 766 &pwm1 {
 767         pinctrl-names = "default";
 768         pinctrl-0 = <&pinctrl_pwm_1>;
 769         #pwm-cells = <3>;
 770 };
 771
 772 /* Verdin PWM_2 */
 773 &pwm2 {
 774         pinctrl-names = "default";
 775         pinctrl-0 = <&pinctrl_pwm_2>;
 776         #pwm-cells = <3>;
 777 };
 778
 779 /* Verdin PWM_3_DSI */
 780 &pwm3 {
 781         pinctrl-names = "default";
 782         pinctrl-0 = <&pinctrl_pwm_3>;
 783         #pwm-cells = <3>;
 784 };
 785
 786 /* TODO: Verdin I2S_1 */
 787
 788 /* TODO: Verdin I2S_2 */
 789
 790 &snvs_pwrkey {
 791         status = "okay";
 792 };
 793
 794 /* Verdin UART_1 */
 795 &uart1 {
 796         pinctrl-names = "default";
 797         pinctrl-0 = <&pinctrl_uart1>;
 798         uart-has-rtscts;
 799 };
 800
 801 /* Verdin UART_2 */
 802 &uart2 {
 803         pinctrl-names = "default";
 804         pinctrl-0 = <&pinctrl_uart2>;
 805         uart-has-rtscts;
 806 };
 807
 808 /* Verdin UART_3, used as the Linux Console */
 809 &uart3 {
 810         pinctrl-names = "default";
 811         pinctrl-0 = <&pinctrl_uart3>;
 812 };
 813
 814 /* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */
 815 &uart4 {
 816         pinctrl-names = "default";
 817         pinctrl-0 = <&pinctrl_uart4>;
 818 };
 819
 820 /* Verdin USB_1 */
 821 &usb3_0 {
 822         fsl,disable-port-power-control;
 823         fsl,over-current-active-low;
 824         pinctrl-names = "default";
 825         pinctrl-0 = <&pinctrl_usb_1_oc_n>;
 826 };
 827
 828 &usb_dwc3_0 {
 829         /* dual role only, not full featured OTG */
 830         adp-disable;
 831         dr_mode = "otg";
 832         hnp-disable;
 833         maximum-speed = "high-speed";
 834         role-switch-default-mode = "peripheral";
 835         srp-disable;
 836         usb-role-switch;
 837
 838         connector {
 839                 compatible = "gpio-usb-b-connector", "usb-b-connector";
 840                 id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
 841                 label = "Type-C";
 842                 pinctrl-names = "default";
 843                 pinctrl-0 = <&pinctrl_usb_1_id>;
 844                 self-powered;
 845                 type = "micro";
 846                 vbus-supply = <&reg_usb1_vbus>;
 847         };
 848 };
 849
 850 /* Verdin USB_2 */
 851 &usb3_1 {
 852         fsl,disable-port-power-control;
 853 };
 854
 855 &usb3_phy1 {
 856         vbus-supply = <&reg_usb2_vbus>;
 857 };
 858
 859 &usb_dwc3_1 {
 860         dr_mode = "host";
 861 };
 862
 863 /* Verdin SD_1 */
 864 &usdhc2 {
 865         assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
 866         assigned-clock-rates = <400000000>;
 867         bus-width = <4>;
 868         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 869         disable-wp;
 870         pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
 871         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
 872         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
 873         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
 874         pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
 875         vmmc-supply = <&reg_usdhc2_vmmc>;
 876 };
 877
 878 /* On-module eMMC */
 879 &usdhc3 {
 880         assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
 881         assigned-clock-rates = <400000000>;
 882         bus-width = <8>;
 883         non-removable;
 884         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 885         pinctrl-0 = <&pinctrl_usdhc3>;
 886         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 887         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 888         status = "okay";
 889 };
 890
 891 &wdog1 {
 892         fsl,ext-reset-output;
 893         pinctrl-names = "default";
 894         pinctrl-0 = <&pinctrl_wdog>;
 895         status = "okay";
 896 };
 897
 898 &iomuxc {
 899         pinctrl_bt_uart: btuartgrp {
 900                 fsl,pins =
 901                         <MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS        0x1c4>,
 902                         <MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX         0x1c4>,
 903                         <MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX         0x1c4>,
 904                         <MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS         0x1c4>;
 905         };
 906
 907         pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
 908                 fsl,pins =
 909                         <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29              0x1c4>; /* SODIMM 256 */
 910         };
 911
 912         pinctrl_ecspi1: ecspi1grp {
 913                 fsl,pins =
 914                         <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO          0x1c4>, /* SODIMM 198 */
 915                         <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI          0x4>,   /* SODIMM 200 */
 916                         <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK          0x4>,   /* SODIMM 196 */
 917                         <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09            0x1c4>; /* SODIMM 202 */
 918         };
 919
 920         /* Connection On Board PHY */
 921         pinctrl_eqos: eqosgrp {
 922                 fsl,pins =
 923                         <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC                            0x3>,
 924                         <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO                          0x3>,
 925                         <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0                      0x91>,
 926                         <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1                      0x91>,
 927                         <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2                      0x91>,
 928                         <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3                      0x91>,
 929                         <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK      0x91>,
 930                         <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL                0x91>,
 931                         <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0                      0x1f>,
 932                         <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1                      0x1f>,
 933                         <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2                      0x1f>,
 934                         <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3                      0x1f>,
 935                         <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL                0x1f>,
 936                         <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK      0x1f>;
 937         };
 938
 939         /* ETH_INT# shared with TPM_INT# (usually N/A) */
 940         pinctrl_eth_tpm_int: ethtpmintgrp {
 941                 fsl,pins =
 942                         <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10            0x1c4>;
 943         };
 944
 945         /* Connection Carrier Board PHY ETH_2 */
 946         pinctrl_fec: fecgrp {
 947                 fsl,pins =
 948                         <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC              0x3>,   /* SODIMM 193 */
 949                         <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO             0x3>,   /* SODIMM 191 */
 950                         <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0        0x91>,  /* SODIMM 201 */
 951                         <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1        0x91>,  /* SODIMM 203 */
 952                         <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2        0x91>,  /* SODIMM 205 */
 953                         <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3        0x91>,  /* SODIMM 207 */
 954                         <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC         0x91>,  /* SODIMM 197 */
 955                         <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL     0x91>,  /* SODIMM 199 */
 956                         <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0        0x1f>,  /* SODIMM 221 */
 957                         <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1        0x1f>,  /* SODIMM 219 */
 958                         <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2        0x1f>,  /* SODIMM 217 */
 959                         <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3        0x1f>,  /* SODIMM 215 */
 960                         <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL     0x1f>,  /* SODIMM 211 */
 961                         <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC        0x1f>,  /* SODIMM 213 */
 962                         <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18             0x1c4>; /* SODIMM 189 */
 963         };
 964
 965         pinctrl_fec_sleep: fecsleepgrp {
 966                 fsl,pins =
 967                         <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC              0x3>,   /* SODIMM 193 */
 968                         <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO             0x3>,   /* SODIMM 191 */
 969                         <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0        0x91>,  /* SODIMM 201 */
 970                         <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1        0x91>,  /* SODIMM 203 */
 971                         <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2        0x91>,  /* SODIMM 205 */
 972                         <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3        0x91>,  /* SODIMM 207 */
 973                         <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC         0x91>,  /* SODIMM 197 */
 974                         <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL     0x91>,  /* SODIMM 199 */
 975                         <MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12             0x1f>,  /* SODIMM 221 */
 976                         <MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13             0x1f>,  /* SODIMM 219 */
 977                         <MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14             0x1f>,  /* SODIMM 217 */
 978                         <MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15             0x1f>,  /* SODIMM 215 */
 979                         <MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16             0x1f>,  /* SODIMM 211 */
 980                         <MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17             0x1f>,  /* SODIMM 213 */
 981                         <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18             0x184>; /* SODIMM 189 */
 982         };
 983
 984         pinctrl_flexcan1: flexcan1grp {
 985                 fsl,pins =
 986                         <MX8MP_IOMUXC_SPDIF_RX__CAN1_RX                 0x154>, /* SODIMM 22 */
 987                         <MX8MP_IOMUXC_SPDIF_TX__CAN1_TX                 0x154>; /* SODIMM 20 */
 988         };
 989
 990         pinctrl_flexcan2: flexcan2grp {
 991                 fsl,pins =
 992                         <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX                0x154>, /* SODIMM 26 */
 993                         <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX                0x154>; /* SODIMM 24 */
 994         };
 995
 996         pinctrl_flexspi0: flexspi0grp {
 997                 fsl,pins =
 998                         <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK          0x1c2>, /* SODIMM 52 */
 999                         <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B       0x82>,  /* SODIMM 54 */
1000                         <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS           0x82>,  /* SODIMM 66 */
1001                         <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00     0x82>,  /* SODIMM 56 */
1002                         <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01     0x82>,  /* SODIMM 58 */
1003                         <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02     0x82>,  /* SODIMM 60 */
1004                         <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03     0x82>,  /* SODIMM 62 */
1005                         <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16          0x82>;  /* SODIMM 64 */
1006         };
1007
1008         pinctrl_gpio1: gpio1grp {
1009                 fsl,pins =
1010                         <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00            0x184>; /* SODIMM 206 */
1011         };
1012
1013         pinctrl_gpio2: gpio2grp {
1014                 fsl,pins =
1015                         <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01            0x1c4>; /* SODIMM 208 */
1016         };
1017
1018         pinctrl_gpio3: gpio3grp {
1019                 fsl,pins =
1020                         <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05            0x184>; /* SODIMM 210 */
1021         };
1022
1023         pinctrl_gpio4: gpio4grp {
1024                 fsl,pins =
1025                         <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06            0x184>; /* SODIMM 212 */
1026         };
1027
1028         pinctrl_gpio5: gpio5grp {
1029                 fsl,pins =
1030                         <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07            0x184>; /* SODIMM 216 */
1031         };
1032
1033         pinctrl_gpio6: gpio6grp {
1034                 fsl,pins =
1035                         <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08            0x184>; /* SODIMM 218 */
1036         };
1037
1038         pinctrl_gpio7: gpio7grp {
1039                 fsl,pins =
1040                         <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03             0x184>; /* SODIMM 220 */
1041         };
1042
1043         pinctrl_gpio8: gpio8grp {
1044                 fsl,pins =
1045                         <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01              0x184>; /* SODIMM 222 */
1046         };
1047
1048         /* Verdin GPIO_9_DSI (pulled-up as active-low) */
1049         pinctrl_gpio_9_dsi: gpio9dsigrp {
1050                 fsl,pins =
1051                         <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25              0x1c4>; /* SODIMM 17 */
1052         };
1053
1054         /* Verdin GPIO_10_DSI */
1055         pinctrl_gpio_10_dsi: gpio10dsigrp {
1056                 fsl,pins =
1057                         <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28             0x1c4>; /* SODIMM 21 */
1058         };
1059
1060         /* Non-wifi MSP usage only */
1061         pinctrl_gpio_hog1: gpiohog1grp {
1062                 fsl,pins =
1063                         <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12           0x1c4>, /* SODIMM 116 */
1064                         <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11           0x1c4>, /* SODIMM 152 */
1065                         <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10           0x1c4>, /* SODIMM 164 */
1066                         <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13            0x1c4>; /* SODIMM 128 */
1067         };
1068
1069         /* USB_2_OC# */
1070         pinctrl_gpio_hog2: gpiohog2grp {
1071                 fsl,pins =
1072                         <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02             0x1c4>; /* SODIMM 187 */
1073         };
1074
1075         pinctrl_gpio_hog3: gpiohog3grp {
1076                 fsl,pins =
1077                         /* CSI_1_MCLK */
1078                         <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15            0x1c4>; /* SODIMM 91 */
1079         };
1080
1081         /* Wifi usage only */
1082         pinctrl_gpio_hog4: gpiohog4grp {
1083                 fsl,pins =
1084                         <MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28             0x1c4>, /* SODIMM 151 */
1085                         <MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29             0x1c4>; /* SODIMM 153 */
1086         };
1087
1088         pinctrl_gpio_keys: gpiokeysgrp {
1089                 fsl,pins =
1090                         <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00             0x1c4>; /* SODIMM 252 */
1091         };
1092
1093         pinctrl_hdmi_hog: hdmihoggrp {
1094                 fsl,pins =
1095                         <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC        0x40000019>,    /* SODIMM 63 */
1096                         <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL    0x400001c3>,    /* SODIMM 59 */
1097                         <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA    0x400001c3>,    /* SODIMM 57 */
1098                         <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD        0x40000019>;    /* SODIMM 61 */
1099         };
1100
1101         /* On-module I2C */
1102         pinctrl_i2c1: i2c1grp {
1103                 fsl,pins =
1104                         <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL                0x400001c6>,    /* PMIC_I2C_SCL */
1105                         <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA                0x400001c6>;    /* PMIC_I2C_SDA */
1106         };
1107
1108         pinctrl_i2c1_gpio: i2c1gpiogrp {
1109                 fsl,pins =
1110                         <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14              0x400001c6>,    /* PMIC_I2C_SCL */
1111                         <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15              0x400001c6>;    /* PMIC_I2C_SDA */
1112         };
1113
1114         /* Verdin I2C_2_DSI */
1115         pinctrl_i2c2: i2c2grp {
1116                 fsl,pins =
1117                         <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL                0x400001c6>,    /* SODIMM 55 */
1118                         <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA                0x400001c6>;    /* SODIMM 53 */
1119         };
1120
1121         pinctrl_i2c2_gpio: i2c2gpiogrp {
1122                 fsl,pins =
1123                         <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16              0x400001c6>,    /* SODIMM 55 */
1124                         <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17              0x400001c6>;    /* SODIMM 53 */
1125         };
1126
1127         /* Verdin I2C_4_CSI */
1128         pinctrl_i2c3: i2c3grp {
1129                 fsl,pins =
1130                         <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL                0x400001c6>,    /* SODIMM 95 */
1131                         <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA                0x400001c6>;    /* SODIMM 93 */
1132         };
1133
1134         pinctrl_i2c3_gpio: i2c3gpiogrp {
1135                 fsl,pins =
1136                         <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18              0x400001c6>,    /* SODIMM 95 */
1137                         <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19              0x400001c6>;    /* SODIMM 93 */
1138         };
1139
1140         /* Verdin I2C_1 */
1141         pinctrl_i2c4: i2c4grp {
1142                 fsl,pins =
1143                         <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL                0x400001c6>,    /* SODIMM 14 */
1144                         <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA                0x400001c6>;    /* SODIMM 12 */
1145         };
1146
1147         pinctrl_i2c4_gpio: i2c4gpiogrp {
1148                 fsl,pins =
1149                         <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20              0x400001c6>,    /* SODIMM 14 */
1150                         <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21              0x400001c6>;    /* SODIMM 12 */
1151         };
1152
1153         /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1154         pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1155                 fsl,pins =
1156                         <MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00              0x184>; /* SODIMM 42 */
1157         };
1158
1159         /* Verdin I2S_2_D_OUT shared with SAI3 */
1160         pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1161                 fsl,pins =
1162                         <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01              0x184>; /* SODIMM 46 */
1163         };
1164
1165         pinctrl_pcie: pciegrp {
1166                 fsl,pins =
1167                         <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19             0x4>,   /* SODIMM 244 */
1168                         <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19           0x1c4>; /* PMIC_EN_PCIe_CLK, unused */
1169         };
1170
1171         pinctrl_pmic: pmicirqgrp {
1172                 fsl,pins =
1173                         <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03            0x1c4>; /* PMIC_INT# */
1174         };
1175
1176         pinctrl_pwm_1: pwm1grp {
1177                 fsl,pins =
1178                         <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT           0x6>;   /* SODIMM 15 */
1179         };
1180
1181         pinctrl_pwm_2: pwm2grp {
1182                 fsl,pins =
1183                         <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT              0x6>;   /* SODIMM 16 */
1184         };
1185
1186         /* Verdin PWM_3_DSI shared with GPIO3_IO20 */
1187         pinctrl_pwm_3: pwm3grp {
1188                 fsl,pins =
1189                         <MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT                0x6>;   /* SODIMM 19 */
1190         };
1191
1192         /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */
1193         pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp {
1194                 fsl,pins =
1195                         <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20              0x184>; /* SODIMM 19 */
1196         };
1197
1198         pinctrl_reg_eth: regethgrp {
1199                 fsl,pins =
1200                         <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20                0x184>; /* PMIC_EN_ETH */
1201         };
1202
1203         pinctrl_sai1: sai1grp {
1204                 fsl,pins =
1205                         <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK             0x96>,  /* SODIMM 38 */
1206                         <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00        0x1d6>, /* SODIMM 36 */
1207                         <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK          0x1d6>, /* SODIMM 30 */
1208                         <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC          0x1d6>, /* SODIMM 32 */
1209                         <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00        0x96>;  /* SODIMM 34 */
1210         };
1211
1212         pinctrl_sai3: sai3grp {
1213                 fsl,pins =
1214                         <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1d6>, /* SODIMM 48 */
1215                         <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK   0x1d6>, /* SODIMM 42 */
1216                         <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x96>,  /* SODIMM 46 */
1217                         <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC  0x1d6>; /* SODIMM 44 */
1218         };
1219
1220         pinctrl_uart1: uart1grp {
1221                 fsl,pins =
1222                         <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS          0x1c4>, /* SODIMM 135 */
1223                         <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS          0x1c4>, /* SODIMM 133 */
1224                         <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX           0x1c4>, /* SODIMM 129 */
1225                         <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX           0x1c4>; /* SODIMM 131 */
1226         };
1227
1228         pinctrl_uart2: uart2grp {
1229                 fsl,pins =
1230                         <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS          0x1c4>, /* SODIMM 143 */
1231                         <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS          0x1c4>, /* SODIMM 141 */
1232                         <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX           0x1c4>, /* SODIMM 137 */
1233                         <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX           0x1c4>; /* SODIMM 139 */
1234         };
1235
1236         pinctrl_uart3: uart3grp {
1237                 fsl,pins =
1238                         <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX           0x1c4>, /* SODIMM 147 */
1239                         <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX           0x1c4>; /* SODIMM 149 */
1240         };
1241
1242         /* Non-wifi usage only */
1243         pinctrl_uart4: uart4grp {
1244                 fsl,pins =
1245                         <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX           0x1c4>, /* SODIMM 151 */
1246                         <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX           0x1c4>; /* SODIMM 153 */
1247         };
1248
1249         pinctrl_usb1_vbus: usb1vbusgrp {
1250                 fsl,pins =
1251                         <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12            0x106>; /* SODIMM 155 */
1252         };
1253
1254         /* USB_1_ID */
1255         pinctrl_usb_1_id: usb1idgrp {
1256                 fsl,pins =
1257                         <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10           0x1c4>; /* SODIMM 161 */
1258         };
1259
1260         /* USB_1_OC# */
1261         pinctrl_usb_1_oc_n: usb1ocngrp {
1262                 fsl,pins =
1263                         <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC           0x1c4>; /* SODIMM 157 */
1264         };
1265
1266         pinctrl_usb2_vbus: usb2vbusgrp {
1267                 fsl,pins =
1268                         <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14            0x106>; /* SODIMM 185 */
1269         };
1270
1271         /* On-module Wi-Fi */
1272         pinctrl_usdhc1: usdhc1grp {
1273                 fsl,pins =
1274                         <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK               0x190>,
1275                         <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD               0x1d0>,
1276                         <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0           0x1d0>,
1277                         <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1           0x1d0>,
1278                         <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2           0x1d0>,
1279                         <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3           0x1d0>;
1280         };
1281
1282         pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1283                 fsl,pins =
1284                         <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK               0x194>,
1285                         <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD               0x1d4>,
1286                         <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0           0x1d4>,
1287                         <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1           0x1d4>,
1288                         <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2           0x1d4>,
1289                         <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3           0x1d4>;
1290         };
1291
1292         pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1293                 fsl,pins =
1294                         <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK               0x196>,
1295                         <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD               0x1d6>,
1296                         <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0           0x1d6>,
1297                         <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1           0x1d6>,
1298                         <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2           0x1d6>,
1299                         <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3           0x1d6>;
1300         };
1301
1302         pinctrl_usdhc2_cd: usdhc2cdgrp {
1303                 fsl,pins =
1304                         <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12              0x1c4>; /* SODIMM 84 */
1305         };
1306
1307         pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1308                 fsl,pins =
1309                         <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12              0x0>;   /* SODIMM 84 */
1310         };
1311
1312         pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1313                 fsl,pins =
1314                         <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22              0x4>;   /* SODIMM 76 */
1315         };
1316
1317         pinctrl_usdhc2: usdhc2grp {
1318                 fsl,pins =
1319                         <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT        0x4>,   /* PMIC_USDHC_VSELECT */
1320                         <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK               0x190>, /* SODIMM 78 */
1321                         <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD               0x1d0>, /* SODIMM 74 */
1322                         <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0           0x1d0>, /* SODIMM 80 */
1323                         <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1           0x1d0>, /* SODIMM 82 */
1324                         <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2           0x1d0>, /* SODIMM 70 */
1325                         <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3           0x1d0>; /* SODIMM 72 */
1326         };
1327
1328         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1329                 fsl,pins =
1330                         <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT        0x4>,
1331                         <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK               0x194>,
1332                         <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD               0x1d4>,
1333                         <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0           0x1d4>,
1334                         <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1           0x1d4>,
1335                         <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2           0x1d4>,
1336                         <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3           0x1d4>;
1337         };
1338
1339         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1340                 fsl,pins =
1341                         <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT        0x4>,
1342                         <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK               0x196>,
1343                         <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD               0x1d6>,
1344                         <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0           0x1d6>,
1345                         <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1           0x1d6>,
1346                         <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2           0x1d6>,
1347                         <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3           0x1d6>;
1348         };
1349
1350         /* Avoid backfeeding with removed card power */
1351         pinctrl_usdhc2_sleep: usdhc2slpgrp {
1352                 fsl,pins =
1353                         <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT        0x0>,
1354                         <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK               0x100>,
1355                         <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD               0x100>,
1356                         <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0           0x100>,
1357                         <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1           0x100>,
1358                         <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2           0x100>,
1359                         <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3           0x100>;
1360         };
1361
1362         pinctrl_usdhc3: usdhc3grp {
1363                 fsl,pins =
1364                         <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B        0x1d1>,
1365                         <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE         0x190>,
1366                         <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5          0x1d0>,
1367                         <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6          0x1d0>,
1368                         <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7            0x1d0>,
1369                         <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0         0x1d0>,
1370                         <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1         0x1d0>,
1371                         <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2         0x1d0>,
1372                         <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3         0x1d0>,
1373                         <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4           0x1d0>,
1374                         <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK             0x190>,
1375                         <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD             0x1d0>;
1376         };
1377
1378         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1379                 fsl,pins =
1380                         <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B        0x1d1>,
1381                         <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE         0x194>,
1382                         <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5          0x1d4>,
1383                         <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6          0x1d4>,
1384                         <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7            0x1d4>,
1385                         <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0         0x1d4>,
1386                         <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1         0x1d4>,
1387                         <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2         0x1d4>,
1388                         <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3         0x1d4>,
1389                         <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4           0x1d4>,
1390                         <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK             0x194>,
1391                         <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD             0x1d4>;
1392         };
1393
1394         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1395                 fsl,pins =
1396                         <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B        0x1d1>,
1397                         <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE         0x196>,
1398                         <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5          0x1d2>,
1399                         <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6          0x1d2>,
1400                         <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7            0x1d2>,
1401                         <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0         0x1d2>,
1402                         <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1         0x1d2>,
1403                         <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2         0x1d2>,
1404                         <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3         0x1d2>,
1405                         <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4           0x1d2>,
1406                         <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK             0x196>,
1407                         <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD             0x1d6>;
1408         };
1409
1410         pinctrl_wdog: wdoggrp {
1411                 fsl,pins =
1412                         <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B          0xc6>;  /* PMIC_WDI */
1413         };
1414
1415         pinctrl_bluetooth_ctrl: bluetoothctrlgrp {
1416                 fsl,pins =
1417                         <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08             0x1c4>; /* WIFI_WKUP_BT */
1418         };
1419
1420         pinctrl_wifi_ctrl: wifictrlgrp {
1421                 fsl,pins =
1422                         <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09             0x1c4>; /* WIFI_WKUP_WLAN */
1423         };
1424
1425         pinctrl_wifi_i2s: wifii2sgrp {
1426                 fsl,pins =
1427                         <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21             0x1d6>, /* WIFI_TX_SYNC */
1428                         <MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21             0x96>,  /* WIFI_RX_DATA0 */
1429                         <MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23             0x1d6>, /* WIFI_TX_BCLK */
1430                         <MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24             0x1d6>; /* WIFI_TX_DATA0 */
1431         };
1432
1433         pinctrl_wifi_pwr_en: wifipwrengrp {
1434                 fsl,pins =
1435                         <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11            0x184>; /* PMIC_EN_WIFI */
1436         };
1437 };