1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2021 Gateworks Corporation
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
13 #include "imx8mp.dtsi"
16 model = "Gateworks Venice GW74xx i.MX8MP board";
17 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
34 device_type = "memory";
35 reg = <0x0 0x40000000 0 0x80000000>;
39 compatible = "gpio-keys";
43 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
50 interrupt-parent = <&gsc>;
57 interrupt-parent = <&gsc>;
64 interrupt-parent = <&gsc>;
71 interrupt-parent = <&gsc>;
76 label = "switch_hold";
78 interrupt-parent = <&gsc>;
84 compatible = "gpio-leds";
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_gpio_leds>;
89 function = LED_FUNCTION_HEARTBEAT;
90 color = <LED_COLOR_ID_GREEN>;
91 gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
93 linux,default-trigger = "heartbeat";
97 function = LED_FUNCTION_STATUS;
98 color = <LED_COLOR_ID_RED>;
99 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
100 default-state = "off";
104 pcie0_refclk: pcie0-refclk {
105 compatible = "fixed-clock";
107 clock-frequency = <100000000>;
111 compatible = "pps-gpio";
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_pps>;
114 gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
117 reg_usb2_vbus: regulator-usb2 {
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_reg_usb2>;
120 compatible = "regulator-fixed";
121 regulator-name = "usb_usb2_vbus";
122 gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
124 regulator-min-microvolt = <5000000>;
125 regulator-max-microvolt = <5000000>;
128 reg_can1_stby: regulator-can1-stby {
129 compatible = "regulator-fixed";
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_reg_can1>;
132 regulator-name = "can1_stby";
133 gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
134 regulator-min-microvolt = <3300000>;
135 regulator-max-microvolt = <3300000>;
138 reg_can2_stby: regulator-can2-stby {
139 compatible = "regulator-fixed";
140 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_reg_can2>;
142 regulator-name = "can2_stby";
143 gpio = <&gpio5 5 GPIO_ACTIVE_LOW>;
144 regulator-min-microvolt = <3300000>;
145 regulator-max-microvolt = <3300000>;
148 reg_wifi_en: regulator-wifi-en {
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_reg_wifi>;
151 compatible = "regulator-fixed";
152 regulator-name = "wl";
153 gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;
154 startup-delay-us = <70000>;
156 regulator-min-microvolt = <3300000>;
157 regulator-max-microvolt = <3300000>;
162 cpu-supply = <®_arm>;
166 cpu-supply = <®_arm>;
170 cpu-supply = <®_arm>;
174 cpu-supply = <®_arm>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_spi1>;
180 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
184 compatible = "tcg,tpm_tis-spi";
185 #address-cells = <0x1>;
188 spi-max-frequency = <36000000>;
192 /* off-board header */
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_spi2>;
196 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_eqos>;
203 phy-mode = "rgmii-id";
204 phy-handle = <ðphy0>;
208 compatible = "snps,dwmac-mdio";
209 #address-cells = <1>;
212 ethphy0: ethernet-phy@0 {
213 compatible = "ethernet-phy-ieee802.3-c22";
220 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_fec>;
222 phy-mode = "rgmii-id";
223 local-mac-address = [00 00 00 00 00 00];
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_flexcan1>;
235 xceiver-supply = <®_can1_stby>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_flexcan2>;
242 xceiver-supply = <®_can2_stby>;
248 "", "", "", "", "", "", "", "",
249 "", "dio0", "", "dio1", "", "", "", "",
250 "", "", "", "", "", "", "", "",
251 "", "", "", "", "", "", "", "";
256 "", "", "", "", "", "", "m2_pin20", "",
257 "", "", "", "", "", "pcie1_wdis#", "pcie3_wdis#", "",
258 "", "", "pcie2_wdis#", "", "", "", "", "",
259 "", "", "", "", "", "", "", "";
264 "", "", "", "", "", "", "m2_rst", "",
265 "", "", "", "", "", "", "", "",
266 "", "", "", "", "", "", "", "",
267 "", "", "", "", "", "", "", "";
272 "", "", "m2_off#", "", "", "", "", "",
273 "", "", "", "", "", "", "", "",
274 "", "", "m2_wdis#", "", "", "", "", "",
275 "", "", "", "", "", "", "", "rs485_en";
280 "rs485_hd", "rs485_term", "", "", "", "", "", "",
281 "", "", "", "", "", "", "", "",
282 "", "", "", "", "", "", "", "",
283 "", "", "", "", "", "", "", "";
287 clock-frequency = <100000>;
288 pinctrl-names = "default", "gpio";
289 pinctrl-0 = <&pinctrl_i2c1>;
290 pinctrl-1 = <&pinctrl_i2c1_gpio>;
291 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
292 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
296 compatible = "gw,gsc";
298 pinctrl-0 = <&pinctrl_gsc>;
299 interrupt-parent = <&gpio4>;
300 interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
301 interrupt-controller;
302 #interrupt-cells = <1>;
303 #address-cells = <1>;
307 compatible = "gw,gsc-adc";
308 #address-cells = <1>;
333 gw,voltage-divider-ohms = <10000 10000>;
340 gw,voltage-divider-ohms = <10000 10000>;
347 gw,voltage-divider-ohms = <22100 1000>;
354 gw,voltage-divider-ohms = <10000 10000>;
361 gw,voltage-divider-ohms = <10000 10000>;
398 gw,voltage-divider-ohms = <10000 10000>;
403 compatible = "gw,gsc-fan";
409 compatible = "nxp,pca9555";
413 interrupt-parent = <&gsc>;
418 compatible = "atmel,24c02";
424 compatible = "atmel,24c02";
430 compatible = "atmel,24c02";
436 compatible = "atmel,24c02";
442 compatible = "dallas,ds1672";
448 clock-frequency = <400000>;
449 pinctrl-names = "default", "gpio";
450 pinctrl-0 = <&pinctrl_i2c2>;
451 pinctrl-1 = <&pinctrl_i2c2_gpio>;
452 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
453 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
457 compatible = "st,lis2de12";
458 pinctrl-names = "default";
459 pinctrl-0 = <&pinctrl_accel>;
461 st,drdy-int-pin = <1>;
462 interrupt-parent = <&gpio1>;
463 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
467 compatible = "microchip,ksz9897";
469 pinctrl-0 = <&pinctrl_ksz>;
470 interrupt-parent = <&gpio4>;
471 interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
474 #address-cells = <1>;
480 phy-mode = "internal";
481 local-mac-address = [00 00 00 00 00 00];
487 phy-mode = "internal";
488 local-mac-address = [00 00 00 00 00 00];
494 phy-mode = "internal";
495 local-mac-address = [00 00 00 00 00 00];
501 phy-mode = "internal";
502 local-mac-address = [00 00 00 00 00 00];
508 phy-mode = "internal";
509 local-mac-address = [00 00 00 00 00 00];
515 phy-mode = "rgmii-id";
527 clock-frequency = <400000>;
528 pinctrl-names = "default", "gpio";
529 pinctrl-0 = <&pinctrl_i2c3>;
530 pinctrl-1 = <&pinctrl_i2c3_gpio>;
531 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
532 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
536 compatible = "nxp,pca9450c";
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_pmic>;
540 interrupt-parent = <&gpio3>;
541 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
545 regulator-name = "BUCK1";
546 regulator-min-microvolt = <720000>;
547 regulator-max-microvolt = <1000000>;
550 regulator-ramp-delay = <3125>;
554 regulator-name = "BUCK2";
555 regulator-min-microvolt = <720000>;
556 regulator-max-microvolt = <1025000>;
559 regulator-ramp-delay = <3125>;
560 nxp,dvs-run-voltage = <950000>;
561 nxp,dvs-standby-voltage = <850000>;
565 regulator-name = "BUCK4";
566 regulator-min-microvolt = <3000000>;
567 regulator-max-microvolt = <3600000>;
573 regulator-name = "BUCK5";
574 regulator-min-microvolt = <1650000>;
575 regulator-max-microvolt = <1950000>;
581 regulator-name = "BUCK6";
582 regulator-min-microvolt = <1045000>;
583 regulator-max-microvolt = <1155000>;
589 regulator-name = "LDO1";
590 regulator-min-microvolt = <1650000>;
591 regulator-max-microvolt = <1950000>;
597 regulator-name = "LDO3";
598 regulator-min-microvolt = <1710000>;
599 regulator-max-microvolt = <1890000>;
605 regulator-name = "LDO5";
606 regulator-min-microvolt = <1800000>;
607 regulator-max-microvolt = <3300000>;
615 /* off-board header */
617 clock-frequency = <400000>;
618 pinctrl-names = "default", "gpio";
619 pinctrl-0 = <&pinctrl_i2c4>;
620 pinctrl-1 = <&pinctrl_i2c4_gpio>;
621 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
622 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
627 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
628 fsl,clkreq-unsupported;
629 clocks = <&pcie0_refclk>;
635 pinctrl-names = "default";
636 pinctrl-0 = <&pinctrl_pcie0>;
637 reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;
641 /* GPS / off-board header */
643 pinctrl-names = "default";
644 pinctrl-0 = <&pinctrl_uart1>;
650 pinctrl-names = "default";
651 pinctrl-0 = <&pinctrl_uart2>;
657 pinctrl-names = "default";
658 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
659 cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
660 rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
664 compatible = "brcm,bcm4330-bt";
665 shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
670 pinctrl-names = "default";
671 pinctrl-0 = <&pinctrl_uart4>;
675 /* USB1 - Type C front panel */
677 pinctrl-names = "default";
678 pinctrl-0 = <&pinctrl_usb1>;
679 fsl,over-current-active-low;
688 /* dual role is implemented but not a full featured OTG */
694 role-switch-default-mode = "peripheral";
698 pinctrl-names = "default";
699 pinctrl-0 = <&pinctrl_usbcon1>;
700 compatible = "gpio-usb-b-connector", "usb-b-connector";
703 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
707 /* USB2 - USB3.0 Hub */
709 vbus-supply = <®_usb2_vbus>;
714 fsl,permanently-attached;
715 fsl,disable-port-power-control;
726 pinctrl-names = "default", "state_100mhz", "state_200mhz";
727 pinctrl-0 = <&pinctrl_usdhc1>;
728 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
729 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
732 vmmc-supply = <®_wifi_en>;
733 #address-cells = <1>;
738 compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
745 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
746 assigned-clock-rates = <400000000>;
747 pinctrl-names = "default", "state_100mhz", "state_200mhz";
748 pinctrl-0 = <&pinctrl_usdhc3>;
749 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
750 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
757 pinctrl-names = "default";
758 pinctrl-0 = <&pinctrl_wdog>;
759 fsl,ext-reset-output;
764 pinctrl-names = "default";
765 pinctrl-0 = <&pinctrl_hog>;
767 pinctrl_hog: hoggrp {
769 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */
770 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */
771 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40000040 /* M2SKT_OFF# */
772 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */
773 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40000040 /* M2SKT_PIN20 */
774 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000040 /* M2SKT_PIN22 */
775 MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x40000150 /* PCIE1_WDIS# */
776 MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */
777 MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */
778 MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */
779 MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */
780 MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */
781 MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */
785 pinctrl_accel: accelgrp {
787 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150
791 pinctrl_eqos: eqosgrp {
793 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
794 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
795 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
796 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
797 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
798 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
799 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
800 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
801 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
802 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
803 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
804 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
805 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
806 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
807 MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */
808 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */
812 pinctrl_fec: fecgrp {
814 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
815 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
816 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
817 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
818 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
819 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
820 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
821 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
822 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
823 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
824 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
825 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
826 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140
827 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140
831 pinctrl_flexcan1: flexcan1grp {
833 MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
834 MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
838 pinctrl_flexcan2: flexcan2grp {
840 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
841 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
845 pinctrl_gsc: gscgrp {
847 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150
851 pinctrl_i2c1: i2c1grp {
853 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
854 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
858 pinctrl_i2c1_gpio: i2c1gpiogrp {
860 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
861 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
865 pinctrl_i2c2: i2c2grp {
867 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
868 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
872 pinctrl_i2c2_gpio: i2c2gpiogrp {
874 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3
875 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3
879 pinctrl_i2c3: i2c3grp {
881 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
882 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
886 pinctrl_i2c3_gpio: i2c3gpiogrp {
888 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3
889 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3
893 pinctrl_i2c4: i2c4grp {
895 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
896 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
900 pinctrl_i2c4_gpio: i2c4gpiogrp {
902 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3
903 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3
907 pinctrl_ksz: kszgrp {
909 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */
910 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */
914 pinctrl_gpio_leds: ledgrp {
916 MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10
917 MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10
921 pinctrl_pcie0: pciegrp {
923 MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x106
927 pinctrl_pmic: pmicgrp {
929 MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140
933 pinctrl_pps: ppsgrp {
935 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140
939 pinctrl_reg_can1: regcan1grp {
941 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154
945 pinctrl_reg_can2: regcan2grp {
947 MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154
951 pinctrl_reg_usb2: regusb2grp {
953 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140
957 pinctrl_reg_wifi: regwifigrp {
959 MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110
963 pinctrl_spi1: spi1grp {
965 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82
966 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82
967 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82
968 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140
972 pinctrl_spi2: spi2grp {
974 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
975 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
976 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
977 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
981 pinctrl_uart1: uart1grp {
983 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
984 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
988 pinctrl_uart2: uart2grp {
990 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
991 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
995 pinctrl_uart3: uart3grp {
997 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
998 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
999 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140
1000 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140
1004 pinctrl_uart3_gpio: uart3gpiogrp {
1006 MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110
1010 pinctrl_uart4: uart4grp {
1012 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
1013 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
1017 pinctrl_usb1: usb1grp {
1019 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140
1023 pinctrl_usbcon1: usb1congrp {
1025 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
1029 pinctrl_usdhc1: usdhc1grp {
1031 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
1032 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
1033 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
1034 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
1035 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
1036 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
1040 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1042 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
1043 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
1044 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
1045 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
1046 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
1047 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
1051 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1053 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
1054 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
1055 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
1056 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
1057 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
1058 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
1062 pinctrl_usdhc3: usdhc3grp {
1064 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
1065 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
1066 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
1067 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
1068 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
1069 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
1070 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
1071 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
1072 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
1073 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
1074 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
1078 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1080 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
1081 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
1082 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
1083 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
1084 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
1085 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
1086 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
1087 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
1088 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
1089 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
1090 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
1094 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1096 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
1097 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
1098 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
1099 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
1100 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
1101 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
1102 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
1103 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
1104 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
1105 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
1106 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
1110 pinctrl_wdog: wdoggrp {
1112 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166