arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2023 Gateworks Corporation
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/leds/common.h>
   8 #include <dt-bindings/phy/phy-imx8-pcie.h>
   9
  10 / {
  11         led-controller {
  12                 compatible = "gpio-leds";
  13                 pinctrl-names = "default";
  14                 pinctrl-0 = <&pinctrl_gpio_leds>;
  15
  16                 led-0 {
  17                         function = LED_FUNCTION_STATUS;
  18                         color = <LED_COLOR_ID_GREEN>;
  19                         gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
  20                         default-state = "on";
  21                         linux,default-trigger = "heartbeat";
  22                 };
  23
  24                 led-1 {
  25                         function = LED_FUNCTION_STATUS;
  26                         color = <LED_COLOR_ID_RED>;
  27                         gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
  28                         default-state = "off";
  29                 };
  30         };
  31
  32         pcie0_refclk: clock-pcie0 {
  33                 compatible = "fixed-clock";
  34                 #clock-cells = <0>;
  35                 clock-frequency = <100000000>;
  36         };
  37
  38         pps {
  39                 compatible = "pps-gpio";
  40                 pinctrl-names = "default";
  41                 pinctrl-0 = <&pinctrl_pps>;
  42                 gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
  43                 status = "okay";
  44         };
  45
  46         reg_usb1_vbus: regulator-usb1 {
  47                 compatible = "regulator-fixed";
  48                 pinctrl-names = "default";
  49                 pinctrl-0 = <&pinctrl_reg_usb1_en>;
  50                 regulator-name = "usb1_vbus";
  51                 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  52                 enable-active-high;
  53                 regulator-min-microvolt = <5000000>;
  54                 regulator-max-microvolt = <5000000>;
  55         };
  56
  57         reg_usb2_vbus: regulator-usb2 {
  58                 compatible = "regulator-fixed";
  59                 pinctrl-names = "default";
  60                 pinctrl-0 = <&pinctrl_reg_usb2_en>;
  61                 regulator-name = "usb2_vbus";
  62                 gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
  63                 enable-active-high;
  64                 regulator-min-microvolt = <5000000>;
  65                 regulator-max-microvolt = <5000000>;
  66         };
  67
  68         reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
  69                 compatible = "regulator-fixed";
  70                 pinctrl-names = "default";
  71                 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
  72                 regulator-name = "VDD_3V3_SD";
  73                 enable-active-high;
  74                 gpio = <&gpio2 19 0>; /* SD2_RESET */
  75                 off-on-delay-us = <12000>;
  76                 regulator-max-microvolt = <3300000>;
  77                 regulator-min-microvolt = <3300000>;
  78                 startup-delay-us = <100>;
  79         };
  80 };
  81
  82 /* off-board header */
  83 &ecspi2 {
  84         pinctrl-names = "default";
  85         pinctrl-0 = <&pinctrl_spi2>;
  86         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
  87         status = "okay";
  88 };
  89
  90 &gpio4 {
  91         gpio-line-names =
  92                 "", "", "", "",
  93                 "", "", "", "",
  94                 "dio1", "", "", "dio0",
  95                 "", "", "pci_usb_sel", "",
  96                 "", "", "", "",
  97                 "", "", "rs485_en", "rs485_term",
  98                 "", "", "", "rs485_half",
  99                 "pci_wdis#", "", "", "";
 100 };
 101
 102 &i2c2 {
 103         clock-frequency = <400000>;
 104         pinctrl-names = "default";
 105         pinctrl-0 = <&pinctrl_i2c2>;
 106         status = "okay";
 107
 108         accelerometer@19 {
 109                 compatible = "st,lis2de12";
 110                 reg = <0x19>;
 111                 pinctrl-names = "default";
 112                 pinctrl-0 = <&pinctrl_accel>;
 113                 st,drdy-int-pin = <1>;
 114                 interrupt-parent = <&gpio4>;
 115                 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
 116         };
 117 };
 118
 119 &pcie_phy {
 120         fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
 121         fsl,clkreq-unsupported;
 122         clocks = <&pcie0_refclk>;
 123         clock-names = "ref";
 124         status = "okay";
 125 };
 126
 127 &pcie {
 128         pinctrl-names = "default";
 129         pinctrl-0 = <&pinctrl_pcie0>;
 130         reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
 131         status = "okay";
 132 };
 133
 134 /* GPS */
 135 &uart1 {
 136         pinctrl-names = "default";
 137         pinctrl-0 = <&pinctrl_uart1>;
 138         status = "okay";
 139 };
 140
 141 /* off-board header */
 142 &uart3 {
 143         pinctrl-names = "default";
 144         pinctrl-0 = <&pinctrl_uart3>;
 145         status = "okay";
 146 };
 147
 148 /* RS232 */
 149 &uart4 {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_uart4>;
 152         status = "okay";
 153 };
 154
 155 /* USB1 - OTG */
 156 &usb3_0 {
 157         pinctrl-names = "default";
 158         pinctrl-0 = <&pinctrl_usb1>;
 159         fsl,over-current-active-low;
 160         status = "okay";
 161 };
 162
 163 &usb3_phy0 {
 164         vbus-supply = <&reg_usb1_vbus>;
 165         status = "okay";
 166 };
 167
 168 &usb_dwc3_0 {
 169         /* dual role is implemented but not a full featured OTG */
 170         adp-disable;
 171         hnp-disable;
 172         srp-disable;
 173         dr_mode = "otg";
 174         usb-role-switch;
 175         role-switch-default-mode = "peripheral";
 176         status = "okay";
 177
 178         connector {
 179                 compatible = "gpio-usb-b-connector", "usb-b-connector";
 180                 pinctrl-names = "default";
 181                 pinctrl-0 = <&pinctrl_usbcon1>;
 182                 type = "micro";
 183                 label = "otg";
 184                 id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
 185         };
 186 };
 187
 188 /* USB2 - USB3.0 Hub */
 189 &usb3_1 {
 190         fsl,permanently-attached;
 191         fsl,disable-port-power-control;
 192         status = "okay";
 193 };
 194
 195 &usb3_phy1 {
 196         vbus-supply = <&reg_usb2_vbus>;
 197         status = "okay";
 198 };
 199
 200 &usb_dwc3_1 {
 201         dr_mode = "host";
 202         status = "okay";
 203 };
 204
 205 /* microSD */
 206 &usdhc2 {
 207         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 208         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 209         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 210         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 211         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 212         bus-width = <4>;
 213         vmmc-supply = <&reg_usdhc2_vmmc>;
 214         status = "okay";
 215 };
 216
 217 &iomuxc {
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pinctrl_hog>;
 220
 221         pinctrl_hog: hoggrp {
 222                 fsl,pins = <
 223                         MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08      0x40000146 /* DIO1 */
 224                         MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11       0x40000146 /* DIO0 */
 225                         MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14      0x40000106 /* PCIE_USBSEL */
 226                         MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x40000106 /* RS485_HALF */
 227                         MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22       0x40000106 /* RS485_EN */
 228                         MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23      0x40000106 /* RS485_TERM */
 229                         MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28      0x40000106 /* PCIE_WDIS# */
 230                 >;
 231         };
 232
 233         pinctrl_accel: accelgrp {
 234                 fsl,pins = <
 235                         MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21      0x150   /* IRQ */
 236                 >;
 237         };
 238
 239         pinctrl_gpio_leds: gpioledgrp {
 240                 fsl,pins = <
 241                         MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01       0x6     /* LEDG */
 242                         MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05      0x6     /* LEDR */
 243                 >;
 244         };
 245
 246         pinctrl_pcie0: pcie0grp {
 247                 fsl,pins = <
 248                         MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29       0x106
 249                 >;
 250         };
 251
 252         pinctrl_pps: ppsgrp {
 253                 fsl,pins = <
 254                         MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03      0x146
 255                 >;
 256         };
 257
 258         pinctrl_reg_usb1_en: regusb1grp {
 259                 fsl,pins = <
 260                         MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12     0x146 /* USB1_EN */
 261                 >;
 262         };
 263
 264         pinctrl_usb1: usb1grp {
 265                 fsl,pins = <
 266                         MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC    0x140 /* USB1_FLT# */
 267                 >;
 268         };
 269
 270         pinctrl_usbcon1: usbcon1grp {
 271                 fsl,pins = <
 272                         MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21      0x140 /* USB1_ID */
 273                 >;
 274         };
 275
 276         pinctrl_reg_usb2_en: regusb2grp {
 277                 fsl,pins = <
 278                         MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12      0x146 /* USBHUB_RST# */
 279                 >;
 280         };
 281
 282         pinctrl_spi2: spi2grp {
 283                 fsl,pins = <
 284                         MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK   0x140
 285                         MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI   0x140
 286                         MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO   0x140
 287                         MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13     0x140
 288                 >;
 289         };
 290
 291         pinctrl_uart1: uart1grp {
 292                 fsl,pins = <
 293                         MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX    0x140
 294                         MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX    0x140
 295                 >;
 296         };
 297
 298         pinctrl_uart3: uart3grp {
 299                 fsl,pins = <
 300                         MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX    0x140
 301                         MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX    0x140
 302                 >;
 303         };
 304
 305         pinctrl_uart4: uart4grp {
 306                 fsl,pins = <
 307                         MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX    0x140
 308                         MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX    0x140
 309                 >;
 310         };
 311
 312         pinctrl_usdhc1: usdhc1grp {
 313                 fsl,pins = <
 314                         MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK        0x190
 315                         MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD        0x1d0
 316                         MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0    0x1d0
 317                         MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1    0x1d0
 318                         MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2    0x1d0
 319                         MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3    0x1d0
 320                 >;
 321         };
 322
 323         pinctrl_usdhc2: usdhc2grp {
 324                 fsl,pins = <
 325                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x190
 326                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d0
 327                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d0
 328                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d0
 329                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d0
 330                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d0
 331                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
 332                 >;
 333         };
 334
 335         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 336                 fsl,pins = <
 337                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x194
 338                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d4
 339                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d4
 340                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d4
 341                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d4
 342                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d4
 343                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
 344                 >;
 345         };
 346
 347         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 348                 fsl,pins = <
 349                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x196
 350                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d6
 351                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d6
 352                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d6
 353                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d6
 354                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d6
 355                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
 356                 >;
 357         };
 358
 359         pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
 360                 fsl,pins = <
 361                         MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B        0x1d0
 362                 >;
 363         };
 364
 365         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 366                 fsl,pins = <
 367                         MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12               0x1c4
 368                 >;
 369         };
 370 };