1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2023 Gateworks Corporation
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/net/ti-dp83867.h>
16 device_type = "memory";
17 reg = <0x0 0x40000000 0 0x80000000>;
21 compatible = "gpio-keys";
25 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
32 interrupt-parent = <&gsc>;
39 interrupt-parent = <&gsc>;
46 interrupt-parent = <&gsc>;
53 interrupt-parent = <&gsc>;
58 label = "switch_hold";
60 interrupt-parent = <&gsc>;
67 cpu-supply = <&buck3_reg>;
71 cpu-supply = <&buck3_reg>;
75 cpu-supply = <&buck3_reg>;
79 cpu-supply = <&buck3_reg>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_eqos>;
85 phy-mode = "rgmii-id";
86 phy-handle = <ðphy0>;
90 compatible = "snps,dwmac-mdio";
94 ethphy0: ethernet-phy@0 {
95 compatible = "ethernet-phy-ieee802.3-c22";
96 pinctrl-0 = <&pinctrl_ethphy0>;
97 pinctrl-names = "default";
99 interrupt-parent = <&gpio3>;
100 interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
101 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
102 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
103 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
104 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
110 clock-frequency = <100000>;
111 pinctrl-names = "default", "gpio";
112 pinctrl-0 = <&pinctrl_i2c1>;
113 pinctrl-1 = <&pinctrl_i2c1_gpio>;
114 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
115 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
119 compatible = "gw,gsc";
121 pinctrl-0 = <&pinctrl_gsc>;
122 interrupt-parent = <&gpio2>;
123 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
124 interrupt-controller;
125 #interrupt-cells = <1>;
126 #address-cells = <1>;
130 compatible = "gw,gsc-adc";
131 #address-cells = <1>;
156 gw,voltage-divider-ohms = <22100 1000>;
163 gw,voltage-divider-ohms = <10000 10000>;
170 gw,voltage-divider-ohms = <10000 10000>;
195 gw,voltage-divider-ohms = <10000 10000>;
220 gw,voltage-divider-ohms = <10000 10000>;
225 compatible = "gw,gsc-fan";
231 compatible = "nxp,pca9555";
235 interrupt-parent = <&gsc>;
240 compatible = "atmel,24c02";
246 compatible = "atmel,24c02";
252 compatible = "atmel,24c02";
258 compatible = "atmel,24c02";
264 compatible = "dallas,ds1672";
269 compatible = "mps,mp5416";
275 regulator-name = "buck1";
276 regulator-min-microvolt = <850000>;
277 regulator-max-microvolt = <1000000>;
284 regulator-name = "buck2";
285 regulator-min-microvolt = <1100000>;
286 regulator-max-microvolt = <1100000>;
293 regulator-name = "buck3";
294 regulator-min-microvolt = <850000>;
295 regulator-max-microvolt = <1000000>;
302 regulator-name = "buck4";
303 regulator-min-microvolt = <1800000>;
304 regulator-max-microvolt = <1800000>;
309 /* OUT2: nvcc_snvs_1p8 */
311 regulator-name = "ldo1";
312 regulator-min-microvolt = <1800000>;
313 regulator-max-microvolt = <1800000>;
320 regulator-name = "ldo2";
321 regulator-min-microvolt = <1000000>;
322 regulator-max-microvolt = <1000000>;
329 regulator-name = "ldo3";
330 regulator-min-microvolt = <2500000>;
331 regulator-max-microvolt = <2500000>;
338 regulator-name = "ldo4";
339 regulator-min-microvolt = <3300000>;
340 regulator-max-microvolt = <3300000>;
348 /* off-board header */
350 clock-frequency = <400000>;
351 pinctrl-names = "default", "gpio";
352 pinctrl-0 = <&pinctrl_i2c2>;
353 pinctrl-1 = <&pinctrl_i2c2_gpio>;
354 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
355 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
359 compatible = "atmel,24c32";
365 /* off-board header */
367 clock-frequency = <400000>;
368 pinctrl-names = "default", "gpio";
369 pinctrl-0 = <&pinctrl_i2c3>;
370 pinctrl-1 = <&pinctrl_i2c3_gpio>;
371 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
372 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
376 /* off-board header */
378 pinctrl-names = "default";
379 pinctrl-0 = <&pinctrl_uart1>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_uart2>;
390 /* off-board header */
392 pinctrl-names = "default";
393 pinctrl-0 = <&pinctrl_uart3>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_usdhc1>;
411 pinctrl-names = "default", "state_100mhz", "state_200mhz";
412 pinctrl-0 = <&pinctrl_usdhc3>;
413 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
414 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&pinctrl_wdog>;
423 fsl,ext-reset-output;
428 pinctrl_eqos: eqosgrp {
430 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
431 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
432 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
433 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
434 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
435 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
436 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
437 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
438 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
439 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
440 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
441 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
442 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
443 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
447 pinctrl_ethphy0: ethphy0grp {
449 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x140 /* RST# */
450 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x150 /* IRQ# */
454 pinctrl_gsc: gscgrp {
456 MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x150 /* IRQ# */
460 pinctrl_i2c1: i2c1grp {
462 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
463 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
467 pinctrl_i2c1_gpio: i2c1gpiogrp {
469 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
470 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
474 pinctrl_i2c2: i2c2grp {
476 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
477 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
481 pinctrl_i2c2_gpio: i2c2gpiogrp {
483 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2
484 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2
488 pinctrl_i2c3: i2c3grp {
490 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
491 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
495 pinctrl_i2c3_gpio: i2c3gpiogrp {
497 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2
498 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2
502 pinctrl_uart1: uart1grp {
504 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
505 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
509 pinctrl_uart2: uart2grp {
511 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
512 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
516 pinctrl_uart3: uart3grp {
518 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
519 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
523 pinctrl_usdhc1: usdhc1grp {
525 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
526 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
527 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
528 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
529 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
530 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
534 pinctrl_usdhc3: usdhc3grp {
536 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
537 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
538 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
539 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
540 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
541 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
542 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
543 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
544 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
545 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
546 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
550 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
552 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
553 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
554 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
555 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
556 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
557 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
558 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
559 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
560 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
561 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
562 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
566 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
568 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
569 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
570 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
571 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
572 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
573 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
574 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
575 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
576 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
577 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
578 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
582 pinctrl_wdog: wdoggrp {
584 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166