arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /*
   3  * Copyright 2021-2022 TQ-Systems GmbH
   4  * Author: Alexander Stein <alexander.stein@tq-group.com>
   5  */
   6
   7 #include "imx8mp.dtsi"
   8
   9 / {
  10         model = "TQ-Systems i.MX8MPlus TQMa8MPxL";
  11         compatible = "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
  12
  13         memory@40000000 {
  14                 device_type = "memory";
  15                 reg = <0x0 0x40000000 0 0x80000000>;
  16         };
  17
  18         /* identical to buck4_reg, but should never change */
  19         reg_vcc3v3: regulator-vcc3v3 {
  20                 compatible = "regulator-fixed";
  21                 regulator-name = "VCC3V3";
  22                 regulator-min-microvolt = <3300000>;
  23                 regulator-max-microvolt = <3300000>;
  24                 regulator-always-on;
  25         };
  26
  27         /* e-MMC IO, needed for HS modes */
  28         reg_vcc1v8: regulator-vcc1v8 {
  29                 compatible = "regulator-fixed";
  30                 regulator-name = "VCC1V8";
  31                 regulator-min-microvolt = <1800000>;
  32                 regulator-max-microvolt = <1800000>;
  33                 regulator-always-on;
  34         };
  35 };
  36
  37 &A53_0 {
  38         cpu-supply = <&buck2_reg>;
  39 };
  40
  41 &flexspi {
  42         pinctrl-names = "default";
  43         pinctrl-0 = <&pinctrl_flexspi0>;
  44         status = "okay";
  45
  46         flash0: flash@0 {
  47                 reg = <0>;
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 compatible = "jedec,spi-nor";
  51                 spi-max-frequency = <80000000>;
  52                 spi-tx-bus-width = <1>;
  53                 spi-rx-bus-width = <4>;
  54         };
  55 };
  56
  57 &i2c1 {
  58         clock-frequency = <384000>;
  59         pinctrl-names = "default", "gpio";
  60         pinctrl-0 = <&pinctrl_i2c1>;
  61         pinctrl-1 = <&pinctrl_i2c1_gpio>;
  62         scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  63         sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  64         status = "okay";
  65
  66         /* NXP SE97BTP with temperature sensor + eeprom */
  67         se97: temperature-sensor-eeprom@1b {
  68                 compatible = "nxp,se97", "jedec,jc-42.4-temp";
  69                 reg = <0x1b>;
  70         };
  71
  72         pmic: pmic@25 {
  73                 reg = <0x25>;
  74                 compatible = "nxp,pca9450c";
  75
  76                 /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
  77                 pinctrl-0 = <&pinctrl_pmic>;
  78                 pinctrl-names = "default";
  79                 interrupt-parent = <&gpio1>;
  80                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
  81
  82                 regulators {
  83                         /* V_0V85_SOC: 0.85 .. 0.95 */
  84                         buck1_reg: BUCK1 {
  85                                 regulator-name = "BUCK1";
  86                                 regulator-min-microvolt = <850000>;
  87                                 regulator-max-microvolt = <950000>;
  88                                 regulator-boot-on;
  89                                 regulator-always-on;
  90                                 regulator-ramp-delay = <3125>;
  91                         };
  92
  93                         /* VDD_ARM */
  94                         buck2_reg: BUCK2 {
  95                                 regulator-name = "BUCK2";
  96                                 regulator-min-microvolt = <850000>;
  97                                 regulator-max-microvolt = <1000000>;
  98                                 regulator-boot-on;
  99                                 regulator-always-on;
 100                                 nxp,dvs-run-voltage = <950000>;
 101                                 nxp,dvs-standby-voltage = <850000>;
 102                                 regulator-ramp-delay = <3125>;
 103                         };
 104
 105                         /* VCC3V3 -> VMMC, ... must not be changed */
 106                         buck4_reg: BUCK4 {
 107                                 regulator-name = "BUCK4";
 108                                 regulator-min-microvolt = <3300000>;
 109                                 regulator-max-microvolt = <3300000>;
 110                                 regulator-boot-on;
 111                                 regulator-always-on;
 112                         };
 113
 114                         /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
 115                         buck5_reg: BUCK5 {
 116                                 regulator-name = "BUCK5";
 117                                 regulator-min-microvolt = <1800000>;
 118                                 regulator-max-microvolt = <1800000>;
 119                                 regulator-boot-on;
 120                                 regulator-always-on;
 121                         };
 122
 123                         /* V_1V1 -> RAM, ... must not be changed */
 124                         buck6_reg: BUCK6 {
 125                                 regulator-name = "BUCK6";
 126                                 regulator-min-microvolt = <1100000>;
 127                                 regulator-max-microvolt = <1100000>;
 128                                 regulator-boot-on;
 129                                 regulator-always-on;
 130                         };
 131
 132                         /* V_1V8_SNVS */
 133                         ldo1_reg: LDO1 {
 134                                 regulator-name = "LDO1";
 135                                 regulator-min-microvolt = <1800000>;
 136                                 regulator-max-microvolt = <1800000>;
 137                                 regulator-boot-on;
 138                                 regulator-always-on;
 139                         };
 140
 141                         /* V_1V8_ANA */
 142                         ldo3_reg: LDO3 {
 143                                 regulator-name = "LDO3";
 144                                 regulator-min-microvolt = <1800000>;
 145                                 regulator-max-microvolt = <1800000>;
 146                                 regulator-boot-on;
 147                                 regulator-always-on;
 148                         };
 149
 150                         /* unused */
 151                         ldo4_reg: LDO4 {
 152                                 regulator-name = "LDO4";
 153                                 regulator-min-microvolt = <800000>;
 154                                 regulator-max-microvolt = <3300000>;
 155                         };
 156
 157                         /* VCC SD IO - switched using SD2 VSELECT */
 158                         ldo5_reg: LDO5 {
 159                                 regulator-name = "LDO5";
 160                                 regulator-min-microvolt = <1800000>;
 161                                 regulator-max-microvolt = <3300000>;
 162                         };
 163                 };
 164         };
 165
 166         pcf85063: rtc@51 {
 167                 compatible = "nxp,pcf85063a";
 168                 reg = <0x51>;
 169         };
 170
 171         at24c02: eeprom@53 {
 172                 compatible = "nxp,se97b", "atmel,24c02";
 173                 read-only;
 174                 reg = <0x53>;
 175                 pagesize = <16>;
 176                 vcc-supply = <&reg_vcc3v3>;
 177         };
 178
 179         m24c64: eeprom@57 {
 180                 compatible = "atmel,24c64";
 181                 reg = <0x57>;
 182                 pagesize = <32>;
 183                 vcc-supply = <&reg_vcc3v3>;
 184         };
 185 };
 186
 187 &usdhc3 {
 188         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 189         pinctrl-0 = <&pinctrl_usdhc3>;
 190         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 191         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 192         bus-width = <8>;
 193         non-removable;
 194         no-sd;
 195         no-sdio;
 196         vmmc-supply = <&reg_vcc3v3>;
 197         vqmmc-supply = <&reg_vcc1v8>;
 198         status = "okay";
 199 };
 200
 201 &wdog1 {
 202         pinctrl-names = "default";
 203         pinctrl-0 = <&pinctrl_wdog>;
 204         fsl,ext-reset-output;
 205         status = "okay";
 206 };
 207
 208 &iomuxc {
 209         pinctrl_flexspi0: flexspi0grp {
 210                 fsl,pins = <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK       0x142>,
 211                            <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B    0x82>,
 212                            <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00  0x82>,
 213                            <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01  0x82>,
 214                            <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02  0x82>,
 215                            <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03  0x82>;
 216         };
 217
 218         pinctrl_i2c1: i2c1grp {
 219                 fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL             0x400001e2>,
 220                            <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA             0x400001e2>;
 221         };
 222
 223         pinctrl_i2c1_gpio: i2c1-gpiogrp {
 224                 fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14           0x400001e2>,
 225                            <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15           0x400001e2>;
 226         };
 227
 228         pinctrl_pmic: pmicirqgrp {
 229                 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08         0x1c0>;
 230         };
 231
 232         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 233                 fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19        0x10>;
 234         };
 235
 236         pinctrl_usdhc3: usdhc3grp {
 237                 fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK          0x194>,
 238                            <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD          0x1d4>,
 239                            <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0      0x1d4>,
 240                            <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1      0x1d4>,
 241                            <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2      0x1d4>,
 242                            <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3      0x1d4>,
 243                            <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4        0x1d4>,
 244                            <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5       0x1d4>,
 245                            <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6       0x1d4>,
 246                            <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7         0x1d4>,
 247                            <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE      0x84>,
 248                            <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B   0x84>;
 249         };
 250
 251         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 252                 fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK          0x194>,
 253                            <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD          0x1d4>,
 254                            <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0      0x1d4>,
 255                            <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1      0x1d4>,
 256                            <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2      0x1d4>,
 257                            <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3      0x1d4>,
 258                            <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4        0x1d4>,
 259                            <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5       0x1d4>,
 260                            <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6       0x1d4>,
 261                            <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7         0x1d4>,
 262                            <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE      0x84>,
 263                            <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B   0x84>;
 264         };
 265
 266         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 267                 fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK          0x194>,
 268                            <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD          0x1d4>,
 269                            <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0      0x1d4>,
 270                            <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1      0x1d4>,
 271                            <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2      0x1d4>,
 272                            <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3      0x1d4>,
 273                            <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4        0x1d4>,
 274                            <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5       0x1d4>,
 275                            <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6       0x1d4>,
 276                            <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7         0x1d4>,
 277                            <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE      0x84>,
 278                            <MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B   0x84>;
 279         };
 280
 281         pinctrl_wdog: wdoggrp {
 282                 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B       0x1c4>;
 283         };
 284 };